HTTP response size is a well-known side channel attack. With the deployment of HTTP/2.0, response size estimation attacks are generally dismissed with the argument that pipelining and response multiplexing prevent eavesdroppers from finding out response sizes. Yet the impact that pipelining and response multiplexing actually have in estimating HTTP response sizes has not been adequately investi...

This article deals with the VLSI architecture of the Floating point and Galois field multiplier, using a technique called Wave-pipelining. Wave -pipelining is a circuit design technique that allows digital synchronous systems to be clocked at rates higher than conventional pipelining techniques. Wave pipelining can improve the throughput of a logic circuit while avoiding some of the overheads o...

FPGAs have advantage over ASICs such as rapid prototyping, in circuit programmability, lower NRE costs and results in more economical designs. In conventional pipelining technique, the operating frequency is increased by dividing the combinational logic into number of stages and registers are introduced between the stages. All the registers are fed with a global clock. This improves the speed o...

Though more diicult to program, distributed-memory parallel machines provide greater scalability than their shared-memory counterparts. Distributed Shared Memory (DSM) systems provide the abstraction of shared memory on a distributed machine. While DSMs provide an attractive programming model, they currently can not eeciently support all classes of scientiic applications. One such class are tho...

Though more difficult to program, distributed-memory parallel machines provide greater scalability than their shared-memory counterparts. Distributed Shared Memory (DSM) systems provide the abstraction of shared memory on a distributed machine. While DSMs provide an attractive programming model, they currently can not efficiently support all classes of scientific applications. One such class ar...

I Research on fundamentals for multiphase pipelining ................................................... 1 II Accomplishments of our previous DOE/DE-FG02-87ER 13798, 9/1/98--8/31/01...... 2 III Lubricated transport of viscous oils. Friction factor efficiency ratio......................... 5 IV Numerical simulation of laminar wavy core flow...........................................................

ÐIn this paper, we examine the effectiveness of a new hardware mechanism, called Register Queues (RQs), which effectively decouples the architected register space from the physical registers. Using RQs, the compiler can allocate physical registers to store live values in the software pipelined loop while minimizing the pressure placed on architected registers. We show that decoupling the archit...

This paper investigates the protocol overhead pipelining between the host and network interface card (NIC). Existing researches into the protocol overhead pipelining assume that protocol overheads in the host and NIC can be naturally pipelined. Our architecture-aware investigation, however, finds a new fact that the host and NIC compete against each other to access the host memory, system bus, ...