a log-domain current-mode true rms-to-dc converter based on a novel synthesis of a simplified current-mode low pass filter and a two-quadrant squarer/divider is presented. the circuit employs floating gate mos (fg-mos) transistors operating in weak inversion region. the converter features low power(<1.5uw), low supply voltage (0.9v), two quadrant input current, immunity from body effect, low ci...

This paper deals with the design of novel sub-1-V bandgap reference circuit using only MOS transistors in 0.18 μm CMOS technology, for a supply voltage of 1.8V. The circuit produces a voltage reference of 466.5 mV at 27C with a temperature coefficient of 28.4 ppm/C in the range of -20 to +120C. The power supply rejection of circuit is -30 dB at 8 KHz and this rejection further increase to -50 d...

In this paper a low-power current-mode RMS-to-DC converter is proposed. The proposed converter includes absolute value circuit, squarer/divider circuit, low-pass filter and square root circuit which employ CMOS transistors operating in weak inversion region. The RMS-to-DC converter has low power consumption (<1μW), low supply voltage (0.9V), wide input range (from 50 nA to 500 nA), low relative...

In this paper, we present an approach for applying two supply voltages to optimize power in CMOS digital circuits under the timing constraints. Given a technology-mapped network, we first analyze the power/delay model and the timing slack distribution in the network. Then a new strategy is developed for timing-constrained optimization issues by making full use of slacks. Based on this strategy,...

   This paper presents a novel design of quaternary logic gates using graphene nanoribbon field effect transistors (GNRFETs). GNRFETs are the alternative devices for digital circuit design due to their superior carrier-transport properties and potential for large-scale processing. In addition, Multiple-valued logic (MVL) is a promising alternative to the conventional binary logic design. Sa...

Noise eeects such as power supply and crosstalk noise can signiicantly impact the performance of deep submicron designs. Existing timing analysis tecniques cannot capture the eeects of noise on the signal/cell delays. This is because these delay eeects are highly input pattern dependent. Therefore, the predicted circuit performance might not reeect the worst-case circuit delay. In this paper, w...

A design technique based on optimizing the supply voltage for simultaneously achieving energy efficiency and temperature variation insensitive circuit performance is proposed in this paper. The supply voltages that suppress the propagation delay variations when the temperature fluctuates are identified for a diverse set of circuits in 180 and 65 nm CMOS technologies. Circuits display temperatur...

Dynamic power is the main source of power consumption in CMOS circuits. It depends on the square of the supply voltage. It may significantly be reduced by scaling down the supply voltage of some computational elements in the circuit, with the penalty of an increase of their execution delay. To reduce the dynamic power consumption, without degrading the performance determined assuming that the c...

abstract introduction: nowadays, the advanced technology of designing electronic circuits in very small size and with very low power consumption has led to development of wearable and implantable medical devices. however, the electronic circuits need power supply that is usually provided by relatively large and heavy batteries. the discharged batteries have to replaced or recharged for long tim...