High performance processors based on pipeline processing play an important role in scientific and engineering computation. However, it is difficult to gain a satisfactory solution when taking both high degree of flexibility of parallel processing and low hardware complexity into account. This paper propose a hybrid pipeline architecture named Jetpipeline that possesses high degree of flexibilit...

This paper presents the results of a quantitative evaluation of the instruction fetch characteristics for media processing. It is commonly known that multimedia applications typically exhibit a significant degree of processing regularity. Prior studies have examined this processing regularity and qualitatively noted that in contrast with general-purpose applications, which tend to retain their ...

Maurer computers for pipelined instruction processing† J. A. BERGSTRA‡ and C. A. MIDDELBURG§ ‡Programming Research Group, University of Amsterdam, P.O. Box 41882, 1009 DB Amsterdam, the Netherlands and Department of Philosophy, Utrecht University, P.O. Box 80126, 3508 TC Utrecht, the Netherlands Email: [email protected] §Programming Research Group, University of Amsterdam, P.O. Box 41882, 100...

In this study, we explore the automaticity of encoding for different facial characteristics and ask whether it is influenced by face familiarity. We used a matching task in which participants had to report whether the gender, identity, race, or expression of two briefly presented faces was the same or different. The task was made challenging by allowing nonrelevant dimensions to vary across tri...

In trace processors, a sequential program is partitioned at run time into “traces.” A trace is an encapsulation of a dynamic sequence of instructions. A processor that uses traces as the unit of sequencing and execution achieves high instruction fetch rates and can support very wide-issue execution engines. We propose a new class of hardware optimizations that transform the instructions within ...

For my MSc project at the Computer Engineering Laboratory at Delft University of Technology I will design and implement a reconfigurable Very Large Instruction Word (VLIW) processing core, for use within the Molen[6, 9] reconfigurable processing paradigm. The Instruction Set Architecture (ISA) used for this processing core will be VEX[2] (VLIW Example), which is loosely modeled on the ISA of th...

Multimedia signal processing, or media processing [1], is the processing of digital multimedia information in a programmable processor. Digital multimedia information includes visual information like images, video, graphics and animation, audio information like voice and music, and textual information like keyboard text and handwriting. With general-purpose computers processing more multimedia ...

Computer-assisted language instruction systems that only perform syntactic processing of input sentences are not able to offer advice on pragmatic aspects of language use, and they cannot handle the variability generally afforded by natural languages to express a given propositional content. This paper describes a solution to this problem implemented as an extension to the existing Japanese tut...