نتایج جستجو برای: processor blocking
تعداد نتایج: 94406 فیلتر نتایج به سال:
This paper develops methods to compute performance measures in a specific type of loss system with multiple classes of customers sharing the same processor. Such systems arise in the modeling of a call center, where the performance measures of interest are blocking the probability of a call and the reneging probability of customers that are put on hold. Expressions for these performance measure...
Non-blocking implementation of shared data objects is a new alternative approach to the problem of designing scalable shared data objects for multiprocessor systems. Non-blocking implementations allow multiple tasks to access a shared object at the same time, but without enforcing mutual exclusion to accomplish this. Since, in non-blocking implementations of shared data objects, one process is ...
We have recently been studying the performance of wavefront algorithms implemented using message passing on 2dimensional logical processor arrays [1,2]. Wavefront algorithms are ubiquitous in parallel computing, since they represent a means of enabling parallelism in computations that contain recurrences. Our particular interest in wavefront algorithms derives from their use in discrete ordinat...
With the wide application of heterogeneous multi-core processor real-time systems, existing analysis methods worst-case response time (WCRT) overestimate blocking information among tasks, resulting in a rather pessimistic estimation. To improve accuracy WCRT, we propose reconstruction-based WCRT method for multi-type directed acyclic graph (DAG) tasks scheduling algorithm(RMDS). The RMDS algori...
Cell Broadband Engine is a new heterogeneous multi-core chip processor designed to provide a high computational power on a single chip. The advent of multi-core chips posed a challenge for a suitable programming and execution model that exploits this new technology. This challenge is greater with Cell, because of the different properties it has compared to other multi-core systems. In this pape...
The problem addressed in this document concerns the coordinated allocation of a finite set of reusable resources to a set of concurrently running processes. These processes execute in a staged manner, and each stage requires a different subset of the system resources for its support. Furthermore, processes will hold upon the resources currently allocated to them until they will secure the neces...
Recently, a rst version of our GEMM-based level 3 BLAS for superscalar type processors was announced. A new feature is the inclusion of DGEMM itself. This DGEMM routine contains inline what we call a level 3 kernel routine, which is based on register blocking. Additionally, it features level 1 cache blocking and data copying of sub-matrix operands for the level 3 kernel. Our other BLAS's which ...
Distributed denial of service is a form cyber-attack that involves sending several network traffic to target system such as DHCP, domain name server (DNS), and HTTP server. The attack aims exhaust computing resources memory the processor by blocking legitimate users from getting access provided Network intrusion prevention ensures security protects attacks. Thus, this paper presents predicitive...
Lower and upper bounds on maximum priority inversion blocking (pi-blocking) are established under distributed multiprocessor real-time semaphore protocols (where resources may be accessed only from specific synchronization processors). Prior work on shared-memory multiprocessor semaphore protocols (which require resources to be accessible from potentially any processor) has established bounds o...
Scheduling in production environments is used as a competitive tool to improve efficiency and respond to customer requests. In this paper, a scheduling problem is investigated in a three-stage flexible flowshop environment with the consideration of blocking and batch processing. This problem has been inspired by the charging and packaging line of a large battery manufacturer. In this environmen...
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