Real-time multiprocessor systems frequently assume that there exists a dedicated processor for task allocation that never fails. This assumption is, however, too strong in the sense that all the physical objects are subject to failure. Moreover, once the dedicated processor fails, the whole multiprocessor system will fail. As a way to solve this problem, we propose a fault-tolerant scheduling a...

We present SSCoP, a novel VLSI scheduling accelerator for multi-processor real-time systems. The co-processor can be used for static scheduling as well as for on-line scheduling. Many diierent policies such as earliest deadline rst, highest value rst, or resource-oriented policies, for example, earliest available time rst, or their combinations can be used. When any on-line scheduling algorithm...

This document describes the processor scheduling framework implemented in the Silicon Graphics IRIX Version 5 operating system. This framework provides the standard features and behavior expected of any UNIX time-sharing system, while adding support for four additional disciplines: a fast-response scheme for lowlatency real-time computing, a time-based regime for throughputoriented real-time co...

preemptively scheduling a set of independent jobs with release time on one processor is a historical problem. in this paper, the same problem has been considered in which objective is to minimize the mean flow time. to prepare a perfect branch-and-bound, some optimality conditions have been represented and they have been compared with the optimality conditions which have been proposed before. o...

Scheduling dependent tasks is one of the most challenging versions of the scheduling problem in parallel and distributed systems. It is known to be computationally intractable in its general form as well as several restricted cases. As a result, researchers have studied restricted forms of the problem by constraining either the task graph representing the parallel tasks or the computer model. A...

-Multicore architecture otherwise called as CMP has many processors packed together on a single chip utilizes hyper threading technology. The main reason for adding large amount of processor core brings massive advancements in parallel computing paradigm. The enormous performance enhancement in multicore platform injects lot of challenges to the task allocation and load balancing on the process...

This paper is concerned with the stochastic modeling of processor scheduling and of queuing due to contention for resources in data base management systems. The processing services rendered in searching the data base and retrieving and processing information are modeled explicitly, as is the algorithm used to schedule these services on the processor. The scheduling of the processor is based on ...

It is shown that the Precedence Constrained K-Processor Scheduling problem is W2]-hard. This means that there does not exist a constant c, such that for all xed K, the Precedence Constrained K-Processor Scheduling problem can be solved in O(n c) time, unless an unlikely collapse occurs in the parameter-ized complexity hierarchy introduced by Downey and Fellows (see 5]). That is, if the problem ...

The article presents an Intellectual Property (IP) for scheduling of multiprocessor systems that is designed using FPGA. The purpose of the IP is to minimize the processor time for scheduling activity by implementing the functionality in hardware. The algorithm implemented clusters the similar tasks on the same processor. Processors not in use are switched to power saving mode and they are only...

— Growing power dissipation due to high performance requirement of processor suggests multicore processor technology, which has become the technology for present and next decade. Research advocates asymmetric multi-core processor system for better utilization of chip real state. However, asymmetric multi core architecture poses a new challenge to operating system scheduler, which traditionally ...