This paper describes a new compression/decompression methodology for using an embedded processor to test the other components of a system-on-a-chip (SoC). The deterministic test vectors for each core are compressed using matrix-based operations that significantly reduce the amount of test data that needs to be stored on the tester. The compressed data is transferred from the tester to the proce...

Many applications in the area of scientiic computing use algorithms with a two-level parallelism based on potential method parallelism and potential system parallelism. In this paper, we investigate the eecient implementation of such algorithms on distributed memory machines. We consider parallel speciications consisting of an upper level of multi-processor tasks each of which having an interna...

For most non-trivial programs it is not satisfactory just to terminate the program with an error message. Consider the situation where the program is a word processor. An error message saying e.g. that some internal register has overflowed is in general not meaningful to a user of such a word processor. Another example is a flight reservation system. Such a system runs over a very long period o...

In present study, in order to improve the performance and reduce the amount of power which is dissipated in heterogeneous multicore processors, the ability of detecting the program execution phases is investigated. The program’s execution intervals have been classified in different phases based on their throughput and the utilization of the cores. The results of implementing the phase detection...

Deterministic Record and Replay [5, 6, 4] addresses the nondeterministic nature of memory access interleavings in executions of parallel codes. The loss of determinism introduces complexities to common processes such as program analysis or debug of software. This is because two accesses to one location by two processors when at least one of them is writing is a data race. For example, consider ...

CMP, chip multiprocessor, embedded processor, embedded DRAM, CPACM MPOC was an ambitious microprocessor project undertaken at Hewlett Packard's Palo Alto Research Lab from about 1998 until early in the year 2001. MPOC was designed to be a single-chip community of identical high-speed RISC processors surrounding a large common storage area. Each processor would have its own clock, cache and prog...

Reactive programs have to react continuously to their inputs. Here the time needed to react with the according output is important. While the synchrony hypothesis takes the view that the program is infinitely fast, real computations take time. Similar to the traditional Worst Case Execution Time (WCET), the Worst Case Reaction Time (WCRT) of a program determines the maximal time for one reactio...

A protocol processor is a programmable processor specifically designed to deal efficiently with protocols. The challenge in designing protocol processors is finding an architecture that is a good compromise between a general purpose processor and a custom, protocol-specific processor. We describe a methodology in which we design both a processor and a program for a network processing applicatio...

A parallel implementation of a divide-and-conquer template (skeleton) is derived systematically from its functional speciication. The implementation makes use of a new processor topology for divide-and-conquer, called N-graph, which suits transputer networks well: there are not more than 4 links per processor, overlapping of computations and communication within a processor is exploited, the pr...

An important and recurring security scenario involves the need to carry out trusted computations in the context of untrusted environments. It is shown how a tamper-detecting interpreter for a programming language – specifically Lisp 1.5 – combined with the use of a secure co-processor can address this problem. The term “tamper-detecting” means that any attempt to corrupt a computation carried o...