This paper proposes a low-power and area-efficient shift register using pulsed latches. The area and power consumption are reduced by replacing flip-flops with pulsed latches. This method solves the timing problem between pulsed latches through the use of multiple non-overlap delayed pulsed clock signals instead of the conventional single pulsed clock signal. The shift register uses a small num...

The triboelectric nanogenerator (TENG) is a promising mechanical energy harvesting technology, but its pulsed output and the instability of input energy sources make associated energy-storage devices necessary for real applications. In this work, feasible and efficient charging of Li-ion batteries by a rotating TENG with pulsed output current is demonstrated. In-depth discussions are made on ho...

This paper describes the Differential Pass Transistor Pulsed Latch (DPTPL) which enhances D-Q delay and reduces power consumption using NMOS pass transistors and feedback PMOS transistors. The proposed flip-flop uses the characteristic of stronger drivability of NMOS transistor than that of transmission gate if the sum of total transistor width is the same. Positive feedback PMOS transistors en...

The high-power generation capability of pulsed mode Silicon Double Drift Region (DDR) IMPATT devices has been studied by using generalized simulation software developed by the authors. The software is based on drift-diffusion modeling scheme, incorporating thermal design. After optimization of the device design, it is observed that a maximum efficiency of 9% with an output power of 15W can be a...

Due to environmental concerns and strict constraints on interference imposed on other networks, the radiated power of emerging pervasive wireless networks needs to be strictly limited, yet without sacrificing acceptable data rates. Pulsed Time-Hopping Ultra-Wide Band (TH-UWB) is a radio technology that has the potential to satisfy this requirement. Although TH-UWB is a multi-user radio technolo...

-In current scenario, VLSI circuit’s greatest challenges is to reduce the power dissipation and surface area so that longer life and high performance achieved to greater extent. The key parameter is threshold voltage to reduce the leakage power. In our proposal, we design low power and high performance JK flip-flop. JK flip-flop is designed with the help of D flip-flop and with some logic gates...