As modern areas of application for coarse-grained reconfigurable systems digital signal processing, multimedia in embedded devices, and wireless communication can be mentioned among others. These fields include different algorithms with varying complexity and speed requirements. In this paper a new highly parameterizable coarse-grained reconfigurable architecture called weakly programmable proc...

This paper introduces a computer architecture, where part of the instruction set architecture (ISA) is implemented on small highly-integrated field-programmable gate arrays (FPGAs). Small FPGAs inside general-purpose processor (CPU) can be used effectively to implement custom or standardised instructions. Our proposed directly address related challenges for high-end CPUs, such would have highes...

In this paper, we present the rationale and design of the Delft reconfigurable and parameterized VLIW processor called ρ-VEX. Its architecture is based on the Lx/ST200 ISA developed by HP and STMicroelectronics. We implemented the processor on an FPGA as an open-source softcore and made it freely available. Using the ρ-VEX, we intend to bridge the gap between general-purpose and application-spe...

This paper describes an approach for adaptive dynamic instruction set extension, tuning embedded processors to specific applications which are going to be executed in their life-time. These new instructions are generated after production. The processor has two modes: training mode and normal mode. Training mode can be done offline or online. The applicationspecific instructions are extracted fr...

Using symbolic feasibility tests during design space exploration of heterogeneous multi-processor systems p. 9 Expression synthesis in process networks generated by LAURA p. 15 Artificial deadlock detection in process networks for ECLIPSE p. 22 Hardware/software interface for multi-dimensional processor arrays p. 28 Casablanca II : implementation of a real-time RISC core for embedded systems p....

To fully exploit the high bandwidth and inherent parallelism of optical memory systems, it is necessary to perform correspondingly parallel computations at or near the interface to the memory system. In this paper, we present a system in which a dynamically reconfigurable processor is built at the optical memory interface. Dynamically reconfigurable processors exploit parallelism at the level o...

In this paper, we present the analysis of applications from the domain of handheld and wearable computing. This analysis is the first step to derive and evaluate design parameters for dynamically reconfigurable processors. We discuss the selection of representative benchmarks for handhelds and wearables and group the applications into multimedia, communications, and cryptography programs. We si...

Future wireless communications networks require flexible modem architectures with high performance. Efficient utilization of application specific flexibility is key to fulfill these requirements. For high throughput a single processor can not provide the necessary computational power. Hence multiprocessor architectures become necessary. This paper presents a multi-processor platform based on a ...