We present a recursive method for generating layout for VLSI chips which combines the flexibility of gate array and standard cell layout with the control and density of custom layout. The method allows seamless integration of hand-drawn and synthesized layout, so that hand layout need only be used where the increase in density is justified. Layout is generated automatically with predictable res...

The paper studies a unit cell mismatch scrambling method for high-resolution unary DAC based on virtual 3-dimensional (3D) layout, to improve its spurious-free dynamic range (SFDR) communication applications. This can be implemented with relatively simple interconnections and circuits, compared that the 2-dimentional (2D) layout.

The simulation-based layout planning of automated material handling systems (AMHS) for microelectronics and semiconductor manufacturing demands adequate simulation models. An approach for measuring and quantifying the AMHS layout performance of alternative planning variants is required. Fraunhofer IPA has developed simulation methods and a three level approach for calculation of AMHS performanc...

One of the well-known evolutionary algorithms inspired by biological evolution is genetic algorithm (GA) that is employed as a robust and global optimization tool to search for the best or near-optimal solution with the search space. In this paper, this algorithm is used to solve unequalsized machines (or intra-cell) layout problems considering pick-up and drop-off (input/output) points. Such p...

In today’s business world, competitiveness defines as an industry leader to drive towards maximum efficiency and it is constantly at the forefront of the companies objectives. Managers across the country are striving to adopt lean manufacturing practices to improve their bottom line cellular manufacturing and it helps to build a variety of products with as little scrap as possible. Layout a fac...

Auto License Plate Detection and Recognition (ALPDR) is required in many industrial fields, including visual surveillance systems vehicle registration control. Even though this field has recently demonstrated high performance according to rapid advances Deep Learning (DL) based technologies, there are still two problems that most related works have not yet solved. One layout-dependent the other...

An important step in today’s Integrated Circuit (IC) manufacturing is optical proximity correction (OPC). While OPC increases the fidelity of pattern transfer to the wafer, it also significantly increases IC layout file size. This has the undesirable side effect of increasing storage, processing, and I.O. times for subsequent steps of mask preparation. To alleviate the growing volume of layout ...

This paper reports a novel methodology and its application to the modeling of a complex 3D geometry on wafer from a layout data. Our modeling method comprises the steps of: drawing a mask layout; transforming the mask layout into a 3D structure by simulating the physical semiconductor process; and extracting device parameters by numerical technique. In order to estimate a 3D structure from the ...