The effect of gate – drain/source underlap ( Lun ) on a narrow band LNA performance has been studied , in 30 nm FinFET using device and mixed mode simulations. Studies are done by maintaining and not maintaining the leakage current (Ioff) of the various devices. LNA circuit with two transistors in a cascode arrangement is constructed and the input impedance, gain and noise-figure have been used...

A two-stage CMOS operational amplifier with both, gain-boosting and indirect current feedback frequency compensation performed by means of regulated cascode amplifiers, is presented. By using quasi-floating-gate transistors (QFGT) the supply requirements, the number of capacitors and the size of the compensation capacitors respect to other Miller schemes are reduced. A prototype was fabricated ...

Absrracl A highly linear CMOS RF amplifier and mixer circuits adopting MOSFET transconductance linearization bv linearlv suoemosine several commonTherefore it is very important to linearize MOSFET transconductance for both RF amplifier and mixer circuits. We have shown that multide eated transistor (MGTR) 111 ~ _ . source FET transistors in parallel, combined with some additional circuit techni...

This paper presents the evaluation of heat generation behavior and related thermal measurement analysis of packaged high-power AlGaN/GaN high electron mobility transistors (HEMTs) cascaded with low-voltage MOSFET and SiC SBD. Since thermal management is extremely important for high power packaging, a hybrid integration of the GaN HEMTs onto a DBC substrate and metal case is proposed. We investi...

In this paper we report the fabrication, design and testing of an uncooled infrared imager based on an active pixel heat balancing technique. The imager is fabricated using a commercial CMOS process plus a simple electrochemical etch stop releasing step. The basic active pixel detector structure consists of a simple cascode CMOS amplifier in which the PMOS devices are built inside a thermally-i...

To proof low voltage techniques are valid in current conveyor design, Bulk driven and composite transistor (self cascode) techniques are used to get high performance results from CCII in low voltage supply. Conventional operational amplifier circuit from literature was our choice as core of the design. Our Focus with using low voltage techniques is study the frequency characteristics of a CCII ...

Cascode CMOS op-amps use a large number of external bias voltages. This results in numerous drawbacks, namely, an area and power overhead, susceptiblity of the bias lines to noise and cross-talk and high sensitivity of the bias point to process variations. In this paper we present a self-biasing technique for folded cascode CMOS op-amps that uses no additional devices and no baas voltages other...

This paper describes a 60-GHz differential power amplifier (PA) designed in a 120-GHz fT 90nm CMOS technology. It consists of three identical differential cascode stages with inter-stage matching implemented by wide-gap coplanar waveguide (CPW) structures and M6M5 plate capacitors. A double-stub network realized by CPWs provides more design freedom for the input matching. Load-pull simulation g...

This paper presents the analysis of hybrid cascode compensation scheme, merged Ahuja and improved Ahuja style compensation methods, which is used in two-stage CMOS operational transconductance amplifiers (OTAs). The open loop signal transfer function is derived to allow the accurate estimation of the poles and zeros. This analytical approach shows that the non-dominant poles and zeros of the hy...