The temporal logic model checking algorithm of Clarke, Emerson, and Sistla [17] is modi ed to represent state graphs using binary decision diagrams (BDDs) [7] and partitioned transition relations [10, 11]. Because this representation captures some of the regularity in the state space of circuits with data path logic, we are able to verify circuits with an extremely large number of states. We de...

A previous hierarchical fault tracing method for combinational circuits which requires only CAD layout data in the CAD-linked electron beam test system is expanded as applicable to sequential circuits. The characteristics in the method remains unchanged that allows us to trace a fault hierarchically from the top level cell to the lowest primitive cell and from the primitive cell to the transist...

Mathematical model of the genetic sequential logic circuit Based on a previously defined model (Bintu et al. 2005), we employed a set of ordinary differential equations to describe the dynamic process of our genetic sequential logic circuit. The circuit’s variables, such as the concentrations of mRNAs and proteins, were plot as functions of time in response to external stimulus. In order to red...

The reliability and the cost of electronic circuits are closely connected to the maximum power dissipated by them. Tools for evaluating the worst case power consumption of sequential circuits is becoming a primal concern for designers of low-power circuits. In the paper the task of estimation of peak sustainable power for CMOS synchronous sequential circuit is considered when its automaton desc...

We address the problem of verifying a retimed circuit. After retiming, some latches in a sequential circuit are repositioned to reduce the clock cycle time and thus the behavior of the combinational portion is changed, Here, we present a novel approach to check the correctness of a retimed circuit according to the dejinition of 3-valued equivalence. This approach is based on our verijication fr...

electric power industry have always try to provide reliable electricity to customers and at the same time decrease system costs. high voltage circuit-breakers are an essential part of the power network. this study has developed a maintenance and replacement scheduling model for high voltage circuit- breakers that minimize maintenance costs while maintaining the acceptable reliability. this mode...

A method to perform diagnostic test generation in sequential circuits by modifying a conventional test generator is presented. The method utilizes circuit netlist modification along with a forced value at a primary input in the modified circuit. Techniques to reduce the computational effort for diagnostic test pattern generation in sequential circuits are also presented. Speed-up of the diagnos...

Behavioral synthesis, which automatically synthesizes an RTL circuit from a sequential program, is one of promising technologies to improve the design productivity. This paper proposes a function call optimization method in behavioral synthesis from large sequential programs with a number of functions. We formulate the optimization problem using integer linear programming. Our experimental resu...

Estimating peak power involves optimization of the circuit’s switching function. The switching of a given gate is not only dependent on the output capacitance of the node, but also heavily dependent on the gate delays in the circuit, since multiple switching events can result from uneven circuit delay paths in the circuit. Genetic spot expansion and optimization are proposed in this paper to es...

TPG for synchronous sequential circuits has received wide attention over the last two decades, yet unlike for (full-scan) combinational circuits, for many sequential benchmark circuits 100% fault efficiency still cannot be reached. This illustrates the complexity of sequential circuit ATPG. The huge search space, which exists during sequential circuit TPG, is the main reason for this complexity...