Device miniaturization is an important part of VLSI design, which refers to reduction in dimension of device by keeping all other characteristic constant. As technology node is moving in submicron region, the performance of the device degrades due to short channel effects and narrow channel effects. The key issues due to these effects are draininduced-barrier– lowering (DIBL), leakage current, ...

In this paper, electrical characteristics of the double gate metal oxide semiconductor field effect transistor (DG MOSFET) and that of gate all around silicon nanowire transistor (GAA SNWT) have been investigated. We have evaluated the variations of the threshold voltage, the subthreshold slope, draininduced barrier lowering, ON and OFF state currents when channel length decreases. Quantum mech...

A simple yet realistic MOS model, namely the a-power law MOS model, is introduced to include the carrier velocity saturation effect, which becomes eminent in short-channel MOSFET’s. The model is an extension of Shockley’s square-law MOS model in the saturation region. Since the model is simple, it can be applied for handling MOSFET circuits analytically and can predict the circuit behavior in t...

We report on the fabrication of short-channel polymer organic thin-film transistors ~OTFTs! using nanoimprint lithography. Currently, there is significant interest in OTFTs due to their potential application in inexpensive, large-area electronics. However, polymer carrier mobilities are typically poor, and thus to increase the OTFT drive current per unit area, there is a need for short-channel ...

High-performance PMOSFETs with sub-50–nm gate-length are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short-channel effects. This vertical double-gate SOI MOSFET features: 1) a transistor channel which is formed on the vertical surfaces of an ultrathin Si fin and controlled by gate electrodes formed on both sides of the fin; 2) two gates which are self-...

Double Gate FinFET devices are suitable for nano electronic circuits due to better scalability, higher on-current (Ion), improved Sub-threshold Slope (SS) and undoped body (no random dopant fluctuation). Body thickness (TSi) increases the gate control over the channel resulting in reduced short channel effects (SCEs). Thin Tsi increases the quantum confinement of charge, resulting increased thr...

A closed-form expression for short-circuit power dissipation of CMOS gates is presented which takes short-channel effects into consideration. The calculation results show good agreement with the SPICE simulation results over wide range of load capacitance and channel length. The change in the short-circuit power, , caused by the scaling in relation to the charging and discharging power, , is di...

The size of integrated devices such as PC, mobiles etc are reducing day by day with multiple operations, all of these is happening because of the scaling down the size of MOSFETs which is the main component in memory, processors and so on. As we scale down the MOSFETs to the nanometer regime the short channel effects arises which degrades the system performance and reliability. Here in this pap...

Triple Material (TM) Double Gate (DG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) with high-k dielectric material as Gate Stack (GS) is presented in this paper. A lightly doped channel has been taken to enhance the device performance and reduce short channel effects (SCEs) such as drain induced barrier lowering (DIBL), sub threshold slope (SS), hot carrier effects (HCEs), channel...