Thangamani.V Kalaignar Karunanidhi Institute of Technology, Chennai Anna University, Kannampalayam(PO),Coimbatore-641402,TamilNadu,India. Contact No.:8675802322, E-mail: [email protected] Abstract The computer memory system has both volatile and non volatile memory. The Volatile memories such as SRAM and DRAM used as a main memory and non volatile memory like flash memory. But in recent days...

Cryptography and Security hardware designing is in continues need for efficient power utilization which is previously achieved by giving a range of trade-off between speed and power consumption. This paper presents the idea of considering subthreshold SRAM memory modules to gain ultra-low-power capable systems. The paper proposes modifying available crypto security hardware architectures to rec...

This paper presents the first results of our work to research and develop new reconfigurable circuits and topologies based on Magnetic RAM (MRAM) memory elements. This work proposes a coarse-grained reconfigurable array using MRAM. A coarse-grained array, where each reconfigurable element computes on 4-bit or larger input words, is more suitable to execute data-oriented algorithms and is more a...

Memories are currently a real bottleneck to design high speed and energy-efficient systems-on-chip. A significant increase of the performance gap between processors and memories is observed. On the other hand, an important proportion of total power is spent on memory systems due to the increasing trend of embedding volatile memory into systems-on-chip. For these reasons, STT-MRAM (Spin-Transfer...

With increased memory capacity usually comes increased bit line parasitice capacitance. This increased bit line capacitance in turn slows down voltage sensing and makes bit line voltage swing energy expensive resulting in slower more energy hungry memories. A full description of the various methods is beyond the scope of this article; instead, the focus is on providing primary developments that...

Memories are most important building blocks in many digital systems. As the Integrated Circuits requirements are growing, the test circuitry must grow as well. There is a need for more efficient test techniques with low power and high speed. Many Memory Built in Self-Test techniques have been proposed to test memories. Compared with combinational and sequential circuits memory testing utilizes ...

To address the limitations of SRAM such as high-leakage and low-density, researchers have explored use of nonvolatile memory (NVM) devices, such as ReRAM (resistive RAM) and STT-RAM (spin transfer torque RAM) for designing on-chip caches. A crucial limitation of NVMs, however, is that their write endurance is low and the large intra-set write variation introduced by existing cache management po...

A Content Addressable Memory (CAM) is hardware search engine in a memory unit that can perform a single clock cycle search operation. Content Addressable Memory is mostly used with the static RAM with the comparison unit to compare data in a single clock cycle leads to more power consumption. This paper proposes a Content Addressable Memory using a NAND cell structure with the comparison unit a...

In this paper, we present a new technique to improve the reliability of SRAMs used in space radiation environments. This technique deals with the SRAM power-bus monitoring by using Built-In Current Sensor (BICS) circuits that detect abnormal current dissipation in the memory power-bus. This abnormal current is the result of a single-event upset (SEU) in the memory and it is generated during the...

The introduction of FinFET technology has turned DRAMs into an interesting candidate to substitute traditional SRAM-based on-chip memory structures (i.e. register file, cache memories). Nevertheless, a major problem to introduce these cells is that they lose their state (i.e. value) over time, and they have to be refreshed. This paper is the first one to propose the implementation of coherent c...