In the past, research on Multiprocessor Systems-on-Chip (MPSoC) has focused mainly on increasing the available processing power on a chip, while less effort was put into specific system-level performance analysis, or into behavior prediction. This paper introduces PAM-SoC, a light-weight performance predictor for MPSoC system-level performance. Being based on Pamela, a static performance predic...

Different intellectual property (IP) cores, including processor and memory, are interconnected to build a typical system-on-chip (SoC) architecture. Larger SoC designs dictate the data communication to happen over the global interconnects. Network-onChip(NoC) architectures have been proposed as a scalable solution to the global communication challenges in nanoscale systemson-chip (SoC) design. ...

This paper illustrates the system on chip (SoC) debugging and analyses its behavior at several test conditions by verifying the functional aspects of the on-chip bus. Here an Advanced High performance bus (AHB) is selected, since the AHB bus signals are difficult to observe as they are deeply embedded in the system on chip and these I/O pins to access these signals is not possible. Hence we emb...

This paper presents an intellectual property (IP)-based system-on-chip (SoC) synthesis framework focusing on how to select IPs from different sources and how to integrate the selected IPs using on-chip buses. In order to synthesize an on-chip bus-based SoC architecture using IPs with imprecise design costs, we propose a possibilistic mixed integer linear programming (PMILP) model, which is conv...

In the system-on-chip (SoC) debugging and performance analysis/optimization, monitoring the on-chip bus signals are necessary. But, such signals are difficult to observe since they are deeply embedded in a SoC and no sufficient I/O pins to access those signals. Therefore, we embed a bus tracer in SoC to capture the bus signals and store them. The stored trace memory can be loaded to the trace a...

This paper illustrates the system on chip (SoC) debugging and analyses its behavior at several test conditions by verifying the functional aspects of the on-chip bus. Here an Advanced High performance bus (AHB) is selected, since the AHB bus signals are difficult to observe as they are deeply embedded in the system on chip and these I/O pins to access these signals is not possible. Hence we emb...

This paper presents an electrical and thermal performance analysis of System-in-a-Package (SiP) memory/logic implementation platform based on ChipLaminate-Chip (CLC) technology. Internal IO interface inside CLC module has been modeled and compared with Stack-Chip (SC) implementation. Thermal analysis, including comparison against Stack-Chip and System-ona-Chip (SoC) is also presented. It is dem...

A high-speed DDR2, DDR2/3, or DDR3 DRAM interface for off-chip memory provides a powerful tool to meet the high-performance demands of new electronic products. However, with advancements come new challenges. The DDR DRAM high-speed interface between the system-on-chip (SoC) and off-chip memory requires specialty circuits. These circuits, often referred to as a physical layer (PHY), comprise hig...

The complexity of the system design is increasing very rapidly as the number of transistors on Integrated Circuits (IC) doubles as per Moore’s law. There is big challenge of testing this complex VLSI circuit, in which whole system is integrated into a single chip called System on Chip (SOC). Cost of testing the SOC is also increasing with complexity. Cost modeling plays a vital role in reductio...

The wavelength routed optical network (WRON) [1] is a promising optical interconnection architecture that can be integrated into a System-on-Chip (SoC) to replace traditional wire-connected on-chip micro-networks which pose severe bandwidth limitations on future super large SoC chips. In this paper, we present the architecture of WRON and generalize the routing schemes based on source address, ...