Built-In Self-Test (BIST) techniques constitute an attractive and practical solution to the problem of testing VLSI circuits and systems. Input vector monitoring concurrent BIST schemes perform testing concurrently with the operation of the circuit. In this paper a novel input vector monitoring concurrent BIST scheme is presented that compares favorably to previously proposed schemes with respe...

Test pattern generator (TPG) is more suitable for built in self test (BIST) structures used for testing of VLSI circuits. The objective of the BIST is to reduce power consumption, switching time and power dissipation without affecting the fault coverage. Low power linear feedback shift register (LPLFSR) is employed for TPG in order to reduce switching activities. This paper presents multiplier,...

Depending on your expectations or claims, mixed-signal BIST could be either fact or fiction. Recognizing facts from fiction is key for the industry to successfully deploy mixed-signal BIST potentials. Is Mixed-Signal-BIST Feasible? Despite the general consensus that considers mixed-signal BIST as a relatively new technology, it has been used as part of high-performance analog design process for...

1. Preface This report presents a compressive study on designing memory BIST. The study covers motivation behind memory BIST, algorithm of different test patterns, surveys of current memory BIST architecture, and discussion of various implementation issues. It is my best intention that this report will serve as a knowledge base for future design in memory BIST. The remainder of this report is o...

We introduce a two-staged Genetic Algorithm for optimizing weighted random pattern testing in a Built-InSelf-Test (BIST) environment. The first stage includes the OBDD-based optimization of input probabilities with regard to the expected test length. The optimization itself is constrained to discrete weight values which can directly be integrated in a BIST environment. During the second stage, ...

This paper presents a new low power BIST TPG scheme for reducing scan transitions. It uses a transition freezing and melting method which is implemented of the transition freezing block and a MUX. When random test patterns are generated from an LFSR, transitions of those patterns satisfy pseudo-random Gaussian distribution. The proposed technique freezes transitions of patterns using a freezing...

and difficult aspects of the circuit design cycle, driving the need for innovative solutions. To this end, researchers have proposed built-in self-test (BIST) as a powerful DFT technique for addressing highly complex VLSI testing problems. BIST designs include on-chip circuitry to provide test patterns and analyze output responses. Performing tests on the chip greatly reduces the need for compl...

Abstract: Testing of VLSI chips are becoming very much complex day by day due to increasing exponential advancement of nano technology. So both front-end and back-end engineers are trying to evolve a system with full testability keeping in mind the possibility of reduced product failures and missed market opportunities. BIST is a design technique that allows a system to test automatically itsel...

The System-On-Chip (SOC) revolution has brought some new challenges to both design and test engineers. The most important challenges of today’s VLSI systems testing are linked to test cost, defect coverage and power dissipation. Implementing a self-testable system may reduce test costs as expensive external high performance test equipment is not required and it may increase defect coverage as t...

A high-level built-in self-test (BIST) synthesis is a process of transforming a behavioral description into a register-transfer level structural description while minimizing BIST overhead. Existing high-level BIST synthesis methods focus on one objective, minimizing either area overhead or test time. Hence, those methods do not render exploration of a large design space, which may result in a l...