Several classes of sequential circuits with combinational test generation complexity have been introduced. However, no general notation is used to define the time complexity of test generation. In this paper, we introduce a new test generation notation that we call τ notation in order to present and clarify the classification of sequential circuits based on the combinational test generation com...

Australia’s Aboriginal and Torres Strait Islander people have very high levels of mental health (and related) problems but relatively few ever receive required treatment. This paper details the development and implementation of an agent-based decision support system, underpinned by dynamic network analysis models and technologies, aimed at assisting an agency concerned with improving outreach t...

Design and construction of a stable current supply with protection circuits are described. The reported circuit provides a high-stable and high-level current variable from 0.5-1.2 A with the protect ion circuits to prevent over load current, voltage and off-range temperature operation. A detailed analysis of the circuit parameters is given and the time behaviors of the load voltage/current and ...

Probabilistic-based methods have been used for designing noise tolerant circuits recently. In these methods, however, there is not any reliability mechanism that is essential for nanometer digital VLSI circuits. In this paper, we propose a novel method for designing reliable probabilistic-based logic gates. The advantage of the proposed method in comparison with previous probabilistic-based met...

As device size scales down, there have been challenges to design conventional analog circuits, such as low voltage headroom and the low intrinsic gain of a device. Although ever-decreasing device channel length in CMOS technology has mainly negative effects on analog circuits, it increases device speed and reduces the power consumption of digital circuits. As a result, time-based signal process...

This paper addresses the issue of reducing test application time in sequential circuits with partial scan using a single clock configuration without freezing the state of the non-scan flip-flops. Experimental results show that this technique significantly reduces test application time. Further, we study the effect of ordering the scan flip-flops on the test vector length and also present a non-...

Detection of chaotic states in the nonlinear chaotic Chua’s oscillatory circuit has been considered. A new approach, based on the concentration measure of the time-frequency (TF) representation, is proposed for determination of the current circuit state. Parameters of the proposed algorithm are studied in details. The algorithm is applied in the case of moderate noisy signal, as well as for bre...

UNLABELLED Time is central to cognition. However, the neural basis for time-dependent cognition remains poorly understood. We explore how the temporal features of neural activity in cortical circuits and their capacity for plasticity can contribute to time-dependent cognition over short time scales. This neural activity is linked to cognition that operates in the present or anticipates events o...