Although the Tunnel Field-Effect Transistor (TFET) is a promising device for ultra-low power CMOS technology due to the ability to reduce power supply voltage and very small off-current, there have been few reports on the control of VT for TFETs. Unfortunately, the TFET needs a different technique to adjust VT than the MOSFET because most of TFETs are assumed to use on SOI substrates. In this p...

This work studies the diameter scaling behavior of broken-band GaSb/InAs vertical nanowire (VNW) Esaki diodes. A top-down fabrication process involving precise reactive-ion etching and alcohol-based digital etch has yielded devices with a tunneling junction below 10 nm. Clear peaks are observed an average peak current density 1MA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlin...

Inter-band tunnel field effect transistors (TFETs) have recently gained a lot of interest because of their ability to eliminate the 60mV/dec sub-threshold slope (STS) limitation in MOSFET. This can result in higher ION-IOFF ratio over a reduced gate voltage range, thus predicting TFETs superior for low supply voltage (VDD  0.5V) operation. Unlike Si and Ge, III-V semiconductors like In0.53Ga0....

The tunnel field-effect transistor (TFET) is a potential candidate for replacing the reverse diode and providing secondary path in whole-chip electrostatic discharge (ESD) protection network. In this paper, ESD characteristics of traditional point TFET, line TFET Ge-source are investigated using technology computer-aided design (TCAD) simulations, an improved TFET-based scheme proposed. It foun...

Abstract In recent years, label-free sensors have been studied extensively for biomolecule detections. Label-free biosensors based on MOSFETs could achieve high detection sensitivity, the subthreshold swing of such cannot break limitation 60 mV Dec −1 due to physical mechanism thermal electron emission. However, less than can be achieved in tunnel FETs working band tunneling (BTBT) mode. Usuall...

In this work, we explore various optimization techniques using bandgap engineering to enhance the performance of tunnel FETs (T-FET) using extensive device simulations. We show that the heterostructure (Si1-γGeγ source or drain) tunnel FET (HT-FET) architecture allows scaling of the device to sub 20 nm gate length regime. N-channel HT-FET is optimized to meet ITRS low standby power and high per...

University Institut Supérieur d’Electronique de Paris (ISEP) – Paris, France Description: Today the circuits dissipate a lot of power without offering performance increase from one technological node to another. It is therefore logical to investigate other solutions than the classical CMOS ones in the attempt to reduce the power consumption. In this context the tunneling FET (TFET) is seen as a...

In this paper review study on different types of Junctionless transistor is promoted. Here a comparative study of SOI, bulk planar, double gate and tunnel Junctionless field effect transistor. It is observed Junctionless transistor exhibits better short channel effects and ON current then inversion mode device. Tunnel Junctionless transistor exhibits the properties of both tunnel FET and Juncti...

The semiconductor industry, governed by the Moore’s law, has achieved the almost unbelievable feat of exponentially increasing performance while lowering the costs for years. The main enabler for this achievement has been the scaling of the CMOS transistor that allowed the manufacturers to pack more andmore functionality into the same chip area. However, it is now widely agreed that the happy d...

As an add-on device option for the ultra-low power CMOS technology, the double-gated vertical-channel Tunnel Field-Effect Transistors (TFETs) of different source configurations are comparatively studied from the perspectives of fabrication and current drivability. While the Top-Source design where the source of the device is placed on the top of the fin makes the fabrication and source engineer...