A denotational semantics and a Hoare programming logic for a subset of the standard hardware description language vhdl are set out here. Both define the behaviour of synchronously clocked vhdl simulators in declarative and compositional style. The logic is proved complete with respect to the denotational semantics and a natural implementation of the logic in prolog as a validation condition gen...

We present a method for modeling and then simulating a mixed hardware/software embedded system implementation in VHDL starting from a high level design representation. In our approach, a complete system description including the communication interfaces is generated automatically in VHDL: Software is modeled by using behavioral VHDL constructs, annotated with timing information derived from bas...

In this paper we present a method for latches and flip flops recognition within VHDL descriptions of hardware systems. Due to the simulation based semantics of VHDL, the existing synthesis tools rely on explicit templates to guarantee memorizing element inference. The approach proposed here is based on a formal representation of VHDL in terms of Interpreted Petri Nets (IPN). After the compilati...

Validation of VHDL descriptions at the early phases of the microelectronic design is one of the most time consuming task design. This paper presents a test vector generation method for behavioral VHDL design. This method analyzes control and dependence flow of VHDL program. We use the cyclomatic complexity, that is a software metric based on a graph associated with the control part of software:...

This paper examines the analog extension to VHDL currently being discussed by the VHDL 1076.1 Working Group and proposes an underlying semantic model for it. The current white papers contain much discussion of syntactic and operational details and an abstraction away from that level of detail is presented here. This semantic model for VHDL-AMS extends our generally accepted semantics for VHDL (...

This paper deals with the problems of system-level specijcation and partitioning in hardwarelsoftware co-design. Itfirst discusses the implication of using VHDL as an implementation-independent specification language. A message passing communication mechanism is proposed to relax the strict synchronization imposed by the simulation-based semantics of VHDL. A partitioning technique is then descr...

Zusammenfassung VHDL-AMS ist eine Hardwarebeschreibungssprache, mit der digitale, analoge und gemischt analogdigitale Systeme simulatorunabhängig modelliert werden können [2], [4], [11], . Der Standardisierungsprozeß der IEEE hat in diesem Jahr einen vorläufigen Abschluß erreicht. Kommerzielle Simulatoren, die VHDL-AMS-Beschreibungen zum Ausgangspunkt haben, befinden sich in der Entwicklung und...

This paper describes FPGA realization of a Fuzzy Temperature Controller (FTC) using VHDL intended for industrial application. The system is built up with four major modules namely fuzzification, inference, implication and defuzzification. The composition method selected for the fuzzy model is the MaxMin composition while the Mamdani Min operator is chosen as the implication method. Each module ...

VHDL-AMS (IEEE 1076.1-1999), an extension to the VHDL, is considered to be a unified language for digital analog, mixed-signal modeling [1],[2]. Although traditionally AMS language is commonly used for behavioral modeling, in this paper special emphasis is given to modeling of mosfet based devices at switch level. We have analyzed VHDL-AMS for switch level modeling on basis of accuracy and resp...

This paper deals with problems of logical level designing, modelling and simulations of digital, combinatorial circuits, which are based on the current mode gates – new digital elements operating with constant, continuous power supply current. For the modelling and simulation purpose some elements of standard Active – VHDL library IEEE1164 were changed. All designed circuits (one and four bits ...