Existing semantic formalisations of the Intel-x86 architecture cover only a small fragment its available features that are relevant for consistency semantics multi-threaded programs as well persistency interfacing with non-volatile memory. We extend these to cover: (1) non-temporal writes, which provide higher performance and used ensure updates flushed memory; (2) reads writes other memory typ...

The x86isa library, incorporated in the ACL2 community books project, provides a formal model of the x86 instruction-set architecture and supports reasoning about x86 machine-code programs. However, analyzing x86 programs can be daunting — even for those familiar with program verification, in part due to the complexity of the x86 ISA. Furthermore, the x86isa library is a large framework, and us...

We present Insight, a framework for binary program analysis and two tools provided with it: CFGRecovery and iii. Insight is intended to be a full environment for analyzing, interacting and verifying executable programs. Insight is able to translate x86, x86-64 and msp430 binary code to our intermediate representation and execute it symbolically in an abstract domain where each variable (registe...

A retrospective evaluation of attitudinal, behavioural and knowledge change among diverse stakeholder groups was conducted in Limpopo Province of South Africa to assess the effectiveness of a series of values clarification (VC) interventions. Telephone and face-to-face interview (193) results revealed that over two-thirds (70.2%) reported behavioural changes and 93.2% reported increased compass...

In most modern processor architectures, difference in data access time for values kept in registers as compared to those in memory is quite high. Thus, compilers should implement efficient register allocation strategies to improve the runtime performance of the code. Register rematerialization is a technique to improve register allocation effectively by improving spill code generation. It is of...

The understanding of instruction set usage in typical DOS/Windows applications plays a very important role in designing high performance x86 compatible microprocessors. This paper presents the tools to such analysis, the analysis results, and their implications on the design of a superscalar processor, based on a RISC core, for efficient x86 instruction execution. The analysis tools include mon...

Continuation-passing style (CPS) is a good abstract representation to use for compilation and optimization: it has a clean semantics and is easily manipulated. We examine how CPS expresses the saving and restoring of registers in source-language procedure calls. In most CPS-based compilers, the context of the calling procedure is saved in a \continuation closure"|a single variable that is passe...

Breaking out of the 1980s RISC mind set, Intel and Hewlett-Packard have designed a new instruction set, IA-64, geared toward the highly parallel processors of the next decade. IA-64 goes beyond previous CISC, RISC, and VLIW instruction sets with a new set of features that its creators call EPIC (explicitly parallel instruction computing). This strategy should give Merced, the first IA-64 chip, ...

For any integer N > 1, we construct feedback with carry shift registers over Z/(N) (N -FCSRs). The case when N is a prime, was investigated by Klapper and Goresky [1, 2]. We present the basic properties of N -FCSRs. We solve the register synthesis problem: given a small number of symbols of a sequence over Z/(N) synthesize the smallest N -FCSR that outputs the sequence.

This paper presents a toolset for model checking x86 executables. The members of the toolset are CodeSurfer/x86, WPDS++, and the Path Inspector. CodeSurfer/x86 is used to extract a model from an executable in the form of a weighted pushdown system. WPDS++ is a library for answering generalized reachability queries on weighted pushdown systems. The Path Inspector is a software model checker buil...