Presented method of on-line detection of overloads and short circuits in digital devices and systems is based on inexpensive overload detectors built into integrated circuits. A prototype 0.8 μm CMOS ASIC successfully verifies this method.

The purpose of this paper is to present a methodology for the evaluation of the Defect Level in an IC design environment. The methodology is based on the extension of Williams-Brown formula to non equiprobable faults, which are collected from the IC layout, using the information on a typical IC process line defect statistics. The concept of weighted fault coverage is introduced, and the Defect ...

This paper describes a high-speed GaAs MESFET digital IC design for optical communication systems. We propose novel circuit configurations of a selector and a static delayed flip-flop which are key elements to perform high-speed digital functions. Employing these new design, the selector IC and static decision IC fabricated with 0.12-μm GaAs MESFET operated up to 44 Gbit/s and 22 Gbit/s, respec...

Proceed 1089-35 IC diagnosis is the process of finding the defect causing a failure at IC test. But what do you do when you have a bad ASIC that does not fail IC test? When you are a systems manufacturer, this puts the quality of your products in jeopardy. Here is the all too common scenario. A board or system test fails, and an ASIC has been diagnosed as being faulty. It has been sent back to ...

The most research on the power consumption of circuits has been concentrated on the switching power and the power dissipated by the leakage current has been relatively minor area. In today’s IC design, one of the key challenges is the increase in power dissipation of the circuit which in turn shortens the service time of battery-powered electronics, reduces the long-term reliability of circuits...

At the input to the calorimeter part of the Level-1 Trigger a Pre-Processor system performs the preprocessing of about 7200 analogue trigger-tower signals. The preprocessing includes digitisation, identi cation of the corresponding bunch-crossing in time (BCID), calibration of the transverse energy, rate monitoring, readout of raw trigger data, and high-speed data transmission to the following ...

5 ASIC Technologies 8 5.1 Full Custom Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.2 Standard Cell ASIC Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.3 Gate Array ASIC Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.4 Sea-of-Gates ASIC Technology . . . . . . . . . . . ....

encountered in ASIC (applicationspecific integrated circuit) developments originate from unclear or incorrectly implemented specifications. To allow independent evaluation of a device’s functionality, the European Space Agency (ESA) normally requests a VHDL model before a company starts the detailed design. This allows ESA or another company to verify the functionality. (For more about ESA and ...

Based on the ASIC layout level simulation of 7 types of adder structures each of four different sizes, i.e. a total of 28 adders, we propose expressions for the width of each of the three regions of the final Carry Propagate Adder (CPA) to be used in parallel multipliers. We also propose the types of adders to be used in each region that would lead to the optimal performance of the hybrid final...

This paper presents an efficient multi-standard decoder for quasicyclic low-density parity-check (QC-LDPC) codes. By employing the configurable multi-bank memory structure, simplified permutation network and multiple pipelined datapaths, the decoder can efficiently support WiMAX and WiFi standards without any structural changes. The offset-min-sumbased row-layered decoding algorithm is adopted ...