A class-AB rail-to-rail CMOS buffer amplifier is proposed and fabricated. The main circuit structure includes a bias circuit, a complementary folded-cascode differential input stage, a common-mode rejection ratio (CMRR) enhancement stage, and a class-AB output stage. With the complementary folded-cascode input stage, high input common-mode range (ICMR) and rail-to-rail output are realized. By u...

Technology scaling has resulted in interconnect delay increasing significantly. Buffer-insertion is a wellknown technique to reduce wire delays of critical signal nets in a circuit. However, the power consumption of buffers has become a critical concern with the increase of the number of buffers. Thanks to a genetic-based algorithm, our work addresses the interconnect delay problem while meetin...

This paper addresses the issues of power dissipation and propagation delay in CMOS buffers driving large capacitive loads and proposes a CMOS buffer design for improving power dissipation at optimized propagation delay. The reduction in power dissipation is achieved by minimizing short circuit power and subthreshold leakage power which is predominant when supply voltage (VDD) and threshold volt...

Polymer solar cells (PSCs) with different anode buffer layers were fabricated to investigate dipoleassisted hole extraction on the performance improvement of PSCs. The power conversion efficiency (PCE) of PSCs was increased from 4.77% to 6.18% with 29.6% improvement due to the increased short circuit current density (Jsc) from 12.00 to 15.65 mA/cm 2 induced by the oriented LiF dipole-assisted h...

A new 2xVDD-tolerant mixed-voltage I/O buffer circuit, realized with only 1xVDD devices in deep-submicron CMOS technology, to prevent transistors against gate-oxide reliability and hot-carrier degradation is proposed. The new proposed 2xVDD-tolerant I/O buffer has been designed and fabricated in a 0.13-lm CMOS process with only 1.2-V devices to serve a 2.5-V/1.2-V mixed-voltage interface, witho...

This paper investigates important problems involved in the design of a CML buffer as well as a chain of tapered CML buffers. A new design procedure to systematically design a chain of tapered CML buffers is proposed. The differential architecture of a CML buffer makes it functionally robust in the presence of environmental noise sources (e.g., crosstalk, power/ground noise). The circuit design ...

Conventional charge pump circuits use a fixed switching frequency that leads to power efficiency degradation for loading less than the rated loading. This paper proposes a level shifter design that also functions as a frequency converter to automatically vary the switching frequency of a dual charge pump circuit according to the loading. The switching frequency is designed to be 25 kHz with 12 ...

The MOS switch with bootstrapped technique is widely used in low-voltage switched-capacitor circuit. The switched-capacitor circuit with the bootstrapped technique could be a dangerous design approach in the nano-scale CMOS process due to the gate-oxide transient overstress. The impact of gate-oxide transient overstress on MOS switch in switchedcapacitor circuit is investigated in this work wit...