We present a SAR ADC with a generalized redundant search algorithm offering the flexibility to relax the requirements on the DAC settling time. The redundancy also allows a digital background calibration, based on a code density analysis, to compensate the capacitor mismatch effects. The total number of capacitors used in this architecture is limited to a half of the one in a classical SAR desi...

This paper describes a digital-domain self-calibration technique for multi-stage analog-to-digital converter (ADC). An accurate calibration is achieved by using a modified radixbased calculation. The equivalent radix-based error term for each stage is extracted by measuring major carry jumps from the ADC transfer curve. A new multiplying digitalto-analog converter (MDAC) architecture using (ins...

Multiple hybrid energy storage systems (HESSs) consisting of batteries and super-capacitors (SCs) are widely used in DC microgrids to compensate for the power mismatch. According their specific characteristics, SCs low-frequency high-frequency mismatches, respectively. This paper proposes a decentralized allocation strategy dynamically forming multiple HESSs aided with novel buffer. The buffer ...

in distribution systems, in order to diminish power losses and keep voltage profiles within acceptable limits, network reconfiguration and capacitor placement are commonly used. in this paper, the hybrid shuffled frog leaping algorithm (hsfla) is used to optimize balanced and unbalanced radial distribution systems by means of a network reconfiguration and capacitor placement. high accuracy and ...

This work proposes a 10 b 200 MS/s 1.8 mm2 83 mW 0.13 μm CMOS ADC based on highly linear integrated capacitors for highquality video system applications such as next-generation DTV and radar vision and wireless communication system applications such as WLAN, WiMax, SDR, LMDS, and MMDS simultaneously requiring low voltage, low power, and small area at high speed. The proposed 3-stage pipeline AD...

System-on-a-chip (SOC) requires integration of analog circuits and digital circuits on a single silicon chip to decrease cost, power dissipation, volume and radiant noise from the data bus on the printed circuit board (PCB). For these mixed-signal intergrated circuits, the standard digital CMOS technology is the best choice in view of cost, power dissipation and implementation convenience. The ...

the increased risk of hemolytic reactions and erythrocyte recovery delay in abo incompatible hematopoietic stem cell transplantation (hsct) is well established. effects of abo incompatibility on transplantation outcomes is evaluated in this study. we prospectively followed 501 patients undergoing allogeneic stem cell transplantation according to abo compatibility groups of minor, major and bidi...