In this paper, two general architectures of Carry Select Adder (CSA) have been introduced for high speed addition. These CSA architectures utilize the hybridized structure of Carry Lookahead Adder (CLA) and Ripple Carry Adder (RCA). In these architectures the critical path delay has been reduced by reducing the number of multiplexer stages. The proposed designs are compared with regular CSA bas...

In many building blocks of microprocessors and digital signal processing chips, adders are frequently available in their critical paths. Adders can also be used for subtraction, multiplication and division. One of the important basic arithmetic operations is addition. There are several structures like Ripple Carry Adder (RCA), Carry Look Ahead Adder (CLA) to perform the addition. Parallel prefi...

RC4 Stream cipher is well known for its simplicity and ease to develope in software. But here, in the proposed design we have heighlighted the modified hardware implémentation of RC4. As RC4 is the most popular stream cipher. The proposed design performs reading and swapping simultaneously in one clock cycle. The proposed design also highlights the adder part which enhances the architecture spe...

Practical issues in the design of power clock generators needed by adiabatic logic circuits are explained. Synchronous and asynchronous power clock generators are designed for an 8-bit adiabatic carry look-ahead adder and the more energy efficient circuit for the power clock generation is determined to be the 2N synchronous power clock generator that exhibits conversion efficiency of 77% at 1 o...

In this paper a novel architecture of multiplier and accumulator (MAC) for high speed arithmetic is presented. The architecture adopts radix-4 modified booth algorithm (MBA) and hybrid carry save adder, in which the accumulator that has the largest delay in MAC was merged into Carry save adder (CSA) block. The performance of final adder block, which determines critical path of the architecture,...

This paper describes a fully static Complementary Metal-Oxide Semiconductor (CMOS) implementation of a Ling type adder. The implementation described herein saves up to one gate delay and always reduces the number of serial transistors in the worst-case (critical) path over the conventional carry look-ahead (CLA) approach with a negligible increase in hardware.

A four-bit adder is simulated using HSPICE in two classic design methods: a ripple-carry adder (RCA) and a carry-look-ahead adder (CLA). All components of the adders are composed of PMOS, NMOS, and capacitors. The propagation delay and power dissipation were measured under different VDD values and different operating temperatures in HSPICE. A comparison of these two metrics were analyzed betwee...

In order to meet the requirements in real time DSP applications MAC unit is required. The speed of the MAC unit determines the overall performance of the system. MAC unit basically consists of Multiplier, adder and an accumulator unit. In most of the cases floating point adder/subtractor and a multiplier are presented in IEEE-754 format for single precision format. In this research work MAC uni...

In this paper, design of two different array multipliers are presented, one by using carry-look-ahead (CLA) logic for addition of partial product terms and another by introducing Carry Save Adder (CSA) in partial product lines. The multipliers presented in this paper were all modeled using VHDL (Very High Speed Integration Hardware Description Language) for 32-bit unsigned data. The comparison ...