A set of CAD tools for the synthesis and layout generation of multiple-valued current-mode CMOS logic (CMCL) circuits is described. The synthesis method is based upon the cost-table method. The general circuit structure, the cost-table functions and the decomposition procedure used in the cost-table synthesis program are explained. The synthesis program is based upon a logically complete set of...

A full-wave analysis of the scattering parameters of a straight-to-bent microstrip line coupling is performed using a FEM technique. The numerical results, showing the influence played by the geometrical parameters of the structure on the electromagnetic coupling, are then employed to derive an equivalent circuit useful to be employed in CAD tools. A third order polynomial approximant useful to...

Partitioning is a critical area of VLSI CAD. In order to build complex digital logic circuits it is often essential to sub-divide a circuit into smaller parts.Circuit partitioning plays an important role in physical design automation of very large scale integration(VLSI)chips.In VLSI.In VLSI circuit partitioning the problem of obtaining minimum cut is of prime importance.To enhance other criter...

We present a formula of short-circuit power dissipation for static CMOS logic gates. By representing shortcircuit current by a piece-wise linear function and considering a current owing from input node to output node through gate capacitances, the accuracy is improved signi cantly. The error of our formula in a CMOS inverter is less than 15% from circuit simulation in many cases of our experime...

In this paper we present a CAD system for logic design using the Atmel 6000 series FPGA circuits. The design input is a textual description in the ABEL hardware description language. This description is compiled into a set of equations. From this set of equations, an internal representation of the digital circuit is generated. Then, the CAD system performs the technology mapping, placement and ...

Computer Aided Design (CAD) tools are commonly adopted in the design, synthesis and simulation of digital circuits. Switch-level simulation, logic synthesis, timing analysis and architecture optimizations are essential CAD tools during digital IC design flow. However, the HDL coding, computation complexity and simulation time overhead makes the design turnaround time much longer. This drawback ...

The roadblock to wide acceptance of asynchronous methodology is poor CAD support. Current asynchronous design tools require a significant re-education of designers, and their capabilities are far behind synchronous commercial tools. This paper considers the testing methodology for a particular subclass of asynchronous circuits (Null Convention Logic or NCL) that entirely relies on conventional ...

| A comparison with synchronous circuits suggests four opportunities for the application of asynchronous circuits: high performance, low power, improved noise and EMC properties, and a natural match with heterogeneous system timing. In this overview article each opportunity is reviewed in some detail, illustrated by examples, compared with synchronous alternatives, and accompanied by numerous p...

FPGA-based platforms offer a unique and challenging platform for implementation of circuit-level timing-error detection and correction logic. If we operate FPGA designs beyond the conservative margins identified by the CAD tools, we can deliver substantial energy and performance improvements. In this paper we develop a strategy for monitoring timing errors in streaming FPGA circuits based on Ra...