This paper focuses on prototyping pausible and gated In this paper, after presenting an overview on the pausible clock based GALS systems on commercial FPGAs. Pausible clock clock based and gated clock based GALS systems in sections II based GLAS systems use an on-chip clock generator to generate and III, the implementation of GALS on commercial FPGA pausible clock pulses whereas gated clock ba...

Crosstalk noise is a crucial factor affecting chip performance in deep submicron technologies. Among all possible crosstalk noise sources, clock is the most common aggressor as well as victim. Crosstalk on clock nets can increase clock jitter, which may degrade significantly the system performance. Besides, in modern chip designs, there is usually more than one clock net, and sometimes even ten...

In animals, networks of clock neurons containing molecular clocks orchestrate daily rhythms in physiology and behavior. However, how various types of clock neurons communicate and coordinate with one another to produce coherent circadian rhythms is not well understood. Here, we investigate clock neuron coupling in the brain of Drosophila and demonstrate that the fly's various groups of clock ne...

| In this paper we investigate reducing the power consumption of a synchronous digital system by minimizing the total power consumed by the clock signals. We construct activity-driven clock trees wherein sections of the clock tree are turned oo by gating the clock signals. Since gating the clock signal implies that additional control signals and gates are needed, there exists a trade-oo between...