Switching the traffic in optical domain has been considerably investigated as a future-proof solution to overcome intrinsic bandwidth bottleneck of electrical switches data center networks (DCNs). However, due lack fast and scalable switch control mechanism, buffers for contention resolution, complicated implementation clock recovery (CDR), practical deployment centers (DCs) remains big challen...

In this paper, we proposed a high data rate, low-power, and large random jitter tolerance wideband signaling (WBS) transceiver for human body channel communication (BCC). At the transmitter part, a spread spectrum clock generator is applied to reduce the electromagnetic emission. Subsequently, the proposed WBS transmitter uses a NRZI encoding scheme to transmit the data. At the receiver part, a...

IBIS-AMI modeling for high-speed serial link systems becomes the de facto standard in the industry. The evolution of IBIS-AMI modeling standard started from a pure THRU channel modeling for NRZ signaling and expanded to the inclusion of crosstalk aggressors, to links containing repeaters, to back-channel transmitter (TX) and receiver (RX) equalizer training process, to the modeling of PAM4 and ...

approvedAs the functionality of digital chips continues to increase dramatically, chipto-chip communication bandwidths must scale accordingly to avoid constraining the overall system performance. Therefore, high speed transceiver design has become an important research topic. In particular, the performance of the circuits that are responsible for timing accuracy are important as bit periods con...

Reception of 4-level pulse amplitude modulation (PAM-4) requires a clock and data recovery (CDR) circuit, typically implemented by PLL-like structure. An essential block in such CDR is the phase detector which should detect whether recovered leads or lags incoming edges. In typical implementations an edge detected sensing waveform crosses threshold level. However, there some ambiguity detecting...

Oscillators based on the SAW (surface acoustic wave) technology in general offer lower noise compared to the conventional crystal oscillators at higher frequencies. VCSO (voltage-controlled SAW oscillator) can be an important component in the phase lock loop (PLL) subsystem for clock and data recovery (CDR), clock smoothing or frequency translation in the SONET/SDH (Synchronous Optical Network ...

The bandwidth demands of modern computing systems have been continually increasing and the recent focus on parallel processing will only increase the demands placed on data communication circuits. As data rates enter the multi-Gb/s range, serial data communication architectures become attractive as compared to parallel architectures. Serial architectures have long been used in fibre optic syste...

ADC-based receivers process the received data in the digital domain, eliminating the need for much of the analog front end. In addition, a feed-forward blind architecture [1,2] eliminates the feedback loop between digital and analog domains so that the ADC and digital CDR can be designed and simulated independently. Previous works [1,2] sampled the incoming data at 2 samples per UI and at 1.45 ...

ADC-based receivers process the received data in the digital domain, eliminating the need for much of the analog front end. In addition, a feed-forward blind architecture [1,2] eliminates the feedback loop between digital and analog domains so that the ADC and digital CDR can be designed and simulated independently. Previous works [1,2] sampled the incoming data at 2 samples per UI and at 1.45 ...

Introduction:It is well-recognized that collimator-detector response (CDR) is the main image blurring factor in SPECT.  In this research, we compensated the images for CDR in molecular SPECT by using STIR reconstruction framework. Methods: To assess resolution recovery capability of the STIR, a phantom containing five point sources along with a micro Derenzo p...