The power consumption of the clock tree dominates over 40% of the total power in high performance VLSI designs. Hence, low power clocking schemes are promising approaches for low power design. We propose energy recovery clocked flip-flops that enable energy recovery from the clock network, resulting in significant energy savings. These flip-flops operate with a single-phase sinusoidal clock whi...

This paper presents a zero-skew gated clock routing technique for VLSI circuits. Gated clock trees include masking gates at the internal nodes of the clock tree, which are selectively turned on and off by the gate control signals during the active and idle times of the circuit modules to reduce the switched capacitance of the clock tree. We construct a clock tree topology based on the locations...

Analysis and Optimization of VLSI Clock Distribution Networks for Skew Variability Reduction. (August 2004) Anand Kumar Rajaram, B.E, Anna University Co–Chairs of Advisory Committee: Dr. Jiang Hu Dr. Rabi Mahapatra As VLSI technology moves into the Ultra-Deep Sub-Micron (UDSM) era, manufacturing variations, power supply noise and temperature variations greatly affect the performance and yield o...

To estimate approximate divergence times of species or species groups with molecular data, we have developed a method of constructing a linearized tree under the assumption of a molecular clock. We present two tests of the molecular clock for a given topology: two-cluster test and branch-length test. The two-cluster test examines the hypothesis of the molecular clock for the two lineages create...

In applications such as design of integrated circuits (chips), it is sometimes required to connect the terminals (receivers) and the central vertex (source) by a weight-minimal tree where the signal delays between the source and the terminals are the same or differ by a minimal value. Simple necessary conditions for existence of the desired tree, heuristic rules for displacement of the terminal...

This paper presents techniques to reduce power consumption in arithmetic logic units (ALUs) while improving performance. This ultimate paradigm in design takes advantage of varying input widths to enable evaluation with partial ALU activation. We will demonstrate partial ALU evaluations have shorter critical paths; this thus enables us to increase clock speed. Shorter clock time means the circu...

With the progress of VLSI technology, delay buffer plays an important role affecting the circuit design and performance. This paper presents the design of low power buffer using clock gating and gated driver tree. Since delay buffers are accessed sequentially, it adopts a gated clock ring counter addressing scheme. The ring counter employs double edge triggered (DET) flip flops instead of tradi...

Vias in Clock Distribution Networks (CDNs) are one of the major sources of signal degradation and delay uncertainty. Also they may impact circuit reliability due to their sensitivity to process variations. With feature size reduction these variations will manifest themselves in adverse effects on clock skew and clock jitter. Therefore, via reduction becomes one of the challenging research areas...

Modern computing system applications or workloads can bring significant non-uniform temperature gradient on-chip, and hence can cause significant temperature uncertainty during clock-tree synthesis. Existing designs of clock-trees have to assume a given time-invariant worst-case temperature map but cannot deal with a set of temperature maps under a set of workloads. For robust clock-tree synthe...