Negative Bias Temperature Instability(NBTI) has become an important reliability concern for ultra-scaled Silicon IC technology with significant implications for both analog and digital circuit design. As the Integrated Circuits (IC) density keeps on increasing with the scaling of CMOS devices in each successive technology generation, stress analysis or reliability concerns mainly Negative Bias ...

Abstract In this paper, we describe a CMOS DC-DC converter with a variable output voltage (8-12V @100mA) for a portable battery-operated system applications. The proposed DC-DC converter is used along with a Pulse-Frequency Modulation (PFM) method and consists of a reference circuit, a feedback resistor, a controller, and an internal oscillator. The integrated DC-DC converter with two external ...

CMOS integrated circuit analysis and design is a fast paced field which deals with many advanced technologies and a difficult skill for many students in a comprehensive first course in Microelectronics. New methods and techniques to help novices learn are needed. In this paper the transistor role concept is used and common individual CMOS transistor roles are identified. Typical circuit and blo...

Now–a-days in digital circuits design high speed, high throughput, small silicon area, and at the same time, lowpower consumption of digital circuit is most important things for digital circuit designers. In this paper a novel design method of a low power digital circuit is discussed, where the GATE DIFFUSION INPUT (GDI) technique has been used for the simultaneous generation of digital logic f...

This paper discusses architectural and circuit-level aspects related to hardware realizations of fuzzy controllers. A brief overview on fuzzy inference methods is given focusing on chip implementation. The singleton or zero-order Sugeno’s method is chosen since it offers a good trade-off between hardware simplicity and control efficiency. The CMOS microcontroller described herein processes info...

In this thesis three novel analog techniques for testing CMOS Integrated circuits are presented. These techniques are based on analog circuits since they offer a number of important advantages compared to standard digital test techniques, such us less silicon area, lower power consumption and high operating speed. Therefore, the proposed techniques can be embedded in the circuit under test, con...

A new architecture for digital implementation of the adaptive equalizer in Class IV partial-response maximum likelihood (PRML) channels employing parallelism and pipelining is described. The architecture was used in a prototype integrated circuit in a 1.2 pm CMOS technology to implement an eight-tap adaptive equalizer and Viterbi sequence detector which consumes a total of 70 mW from a 3.3 V su...

ETRI Journal, Volume 29, Number 1, February 2007 A new low-voltage CMOS interface circuit with digital output for piezo-resistive transducer is proposed. An input current sensing configuration is used to detect change in piezo-resistance due to applied pressure and to allow lowvoltage circuit operation. A simple 1-bit first-order deltasigma modulator is used to produce an output digital bitstre...

A CMOS image sensor with pixel level analog to digital conversion is presented. Each 13.8μm x 13.8μm pixel area contains a photodiode and a dynamic comparator using the maximum voltage swing available (0V 1.8V). The comparator does not need any bias current and is insensitive to fabrication process variations. Also a digital to analog converter (DAC) is used to deliver a voltage reference in or...