A novel high-speed and low-voltage CMOS level shifter circuit is proposed. The proposed circuit is suitable for block-level dynamic voltage and frequency scaling (DVFS) environment or multiple-clock and multiple-power-domain logic blocks. In order to achieve high performance in a chip consisting of logic blocks having different VDD voltages, the proposed circuit uses the circuit techniques to r...

In recent years, low power circuit design has been an important issue in VLSI design areas. Adiabatic logics, which dissipate less power than static CMOS logic, have been introduced as a promising new approach in low power circuit design. energy. This paper proposes an Adder circuit based on energy efficient two-phase clocked adiabatic logic. A simulative investigation on the proposed 1-bit ful...

This paper shows how the application of a CMOS ternary logic is useful in the realisation of Delay Insensitive (01) asynchronous circuits. It is shown that fully DI asynchronous circuits are obtained with a ternary handshake protocol which employs the third logic level as idle state of the asynchronous interface. The advantages obtained are a dramatic reduction of the communication requirement ...

The objective of this work is to develop a new logic circuit synthesis and optimization procedure for arbitrary logic function. Following the procedure, we may get a new high performance logic circuit family, which has low power consumption, low power-delay product, area efficiency and suitable for low supply voltage. The new logic family based upon the proposed design procedures has certain ad...

Different logic families have been proposed from several years to improve the performance of the high speed circuits. Mostly used logic family is CMOS which requires equal number of nMOS and pMOS transistor but in some application it may be required to reduce the area. Pseudo nMOS logic is one of the alternative for that .In this paper, NOR-XOR, NAND-XOR and other combinational circuit using ps...

As the operating supply voltage for commercial CMOS devices falls below 2 V, research activities are underway to develop CMOS integrated circuits that can operate at supply voltages well under 1 V. Although dramatic power reductions can be achieved using low supply voltages in high performance applications, the increased subthreshold leakage that results when transistor threshold voltages are l...

AbstructA novel BiCMOS full-swing circuit technique with superior performance over CMOS down to 1.5 V is proposed. A conventional noncomplementary BiCMOS process is used. The proposed pull-up configuration is based on a capacitively coupled feedback circuit. Several pull-down options were examined and compared, and the results are reported. Several cells were implemented using the novel circuit...

Abstract— Quantum dot Cellular Automata (QCA) is anticipated to allow for extremely dense nano-scale design and implementation of logic circuit over the Complementary Metal Oxide Semiconductor (CMOS). QCA has been considered as a promising alternative to CMOS technology for its lower power consumption, higher scale integration and higher switching frequency. Moreover, the basic element in QCA i...