A delay-locked loop (DLL) based built-in self test (BIST) circuit has been designed with a 0.18 μ m TSMC process (CM018) to test chip I/O speeds, specifically, the setup and hold times of I/O registers or buffers. The frequency lock range of the DLL is 150-600 MHz (4x). The DLL uses a combined phase detector and charge pump circuit (PD+CP) for increased speed and reduced jitter. The DLL also em...

We experimentally investigate the RF linewidth and timing jitter over a wide range of delay tuning in a self-mode-locked two-section quantum dash lasers emitting at ~ 1.55μm and operating at ~ 21 GHz repetition rate subject to single and dual optical feedback into gain section. Various feedback conditions are investigated and optimum levels determined for narrowest linewidth and reduced timing ...

An ASIC design of Dual Edge Triggered Phase Detector(DET PD) for Delay locked loop(DLL) and Phase locked loop(PLL) applications is proposed in this paper.The proposed DET PD has high locking speed and less jitter. The designs are based on TSPC flip flop logic, which overcomes the issue of narrow capture range. The Double edge triggered phase detector dissipates less power than conventional desi...

The input frequency limit of the conventional zero-crossing digital phase-locked loop (ZCDPLL) is due to the operating time of the digital circuitry inside the feedback loop. A solution that has been previously suggested is the introduction of a time delay in the feedback path of the loop to allow the digital circuits to complete their sample processing before the next sample is received. Howev...

In this paper, a Delay-Locked Loop (DLL) based clock generator is designed which can be used mainly for dynamic frequency scaling. This DLL-based clock generator is found to have low-jitter and can provide the system clock with frequencies in the range of 0.5 to 8 times of reference clock, depending on the workload of the EISC processor. This proposed analog self-calibration method and a phase ...

A four-phase all-digital delay-locked loop (ADDLL) with a de-skew circuit for NAND Flash high-speed interfaces is proposed. The proposed adopts fall-edge-judgment phase adjuster and three-stage digitally controlled delay line to align the system input clock 0∘ output of DLL over wide frequency range, thus solving offset caused by skew. parallel-cascade configuration solve variable alignment pro...