This paper describes the design of an All-Digital Phase Locked Loop (AD-PLL) for wireless applications in the WiMAX 3.3– 3.8 GHz bandwidth. The time/digital converter (TDC) sets the in-band noise and it may be responsible for the presence of spurious tones at the PLL output. The TDC is implemented as a delay-locked loop (DLL) to be insensitive to process spreads and it uses a lead-lag phase det...

A data driven multi-channel Time-to-Digital Converter (TDC) circuit with programmable resolution (25ps 800ps bin) has been implemented in a 0.25um CMOS technology. An on-chip PLL is used for clock multiplication up to 320MHz from an external 40MHz reference. A 32 element Delay Locked Loop (DLL) performs time interpolation down to 98ps. Finally, finer time interpolation is obtained using an on-c...

Dual threshold voltages domino design methodology utilizes low threshold voltages for all transistors that can switch during the evaluate mode and utilizes high threshold voltages for all transistors that can switch during the pre charge modes. We employed standby switch can strongly turn off all of the high threshold voltage transistors which enhances the effectiveness of a dual threshold volt...

Two types of coherent delay-locked loops (DLL) are considered in this paper as delay trackers in multiuser CDMA receivers. The rst approach is based on the parallel interference cancellation (PIC) method. PIC based delay trackers require the estimation of channel parameters and data symbols of all users to construct the multiple-access interference (MAI) estimates. The other method is based on ...

The objective of the thesis is to address the problem of clock skew between two different clock domains in modern day microprocessors due to the process, voltage and temperature (PVT) variations. In order to mitigate the misalignment of the clocks in the different clock domains, a delay line is added in all but the reference clock domain. These delay lines add or subtract the delay (as necessar...

Abstract A high-resolution clock phase shifter is implemented to adjust the of multiple clocks at 40 MHz, 80 or 640 MHz in ALTIROC chip. The has a coarse-phase and fine-phase achieve step size 97.7 ps an adjustable range 25 ns. fine delay unit based on Delay Locked Loop (DLL) operating MHz. fabricated 130 nm CMOS process. area 725 µm × 248 µm. Differential Non-Linearity (DNL) Integral (INL) are...

Multipath propagation, multiple access interference and non-line of sight propagation, etc. have impeded the accuracy in mobile data measurements. Multiuser receivers in asynchronous Code Division Multiple Access (CDMA) systems require the knowledge of several parameters such as timing delay between users. In this paper, the problem of time delay estimation for CDMA systems is examined by propo...

A 4Gb/s power and area efficient clock/data recovery (CDR) circuit is proposed. Fully-differential design is employed to reject any common mode noises and to significantly reduce power/ground bounce. An analog dual delay-locked loop (DLL) architecture continuously aligns the clock sampling edge to the center of incoming data eye-opening. A self-correcting function prevents the phase capture ran...

In scaled CMOS processes, the single-event effects generate missing output pulses in Delay-Locked Loop (DLL). Due to its effective sequence detection of the missing pulses in the proposed Error Correction Circuit (ECC) and its portability to be applied to any DLL type, the ECC mitigates the impact of single-event effects and completes its operation with less design complexity without any concer...

The objective of the thesis is to address the problem of clock skew between two different clock domains in modern day microprocessors due to the process, voltage and temperature (PVT) variations. In order to mitigate the misalignment of the clocks in the different clock domains, a delay line is added in all but the reference clock domain. These delay lines add or subtract the delay (as necessar...