Sigma-Delta (∑-∆) analog to digital converters are well known for its use in high accuracy wireless communication applications. It is alternative for low power, high resolution (greater than 12 bits) converters, which can be ultimately integrated on digital signal Processor ICs. In this work Over Sampling concept is used to address the problem of power dissipation and noise in ADCs. In this pap...

This work presents a novel noise-shaping cascaded sigma-delta modulator that incorporates two stages. The first stage is realized by low-order single bit architecture, while the second stage is realized by a high-order feed-forward multi-bit architecture. Moreover, the error cancellation schemes can be added in the digital circuit part to cancel the coarse quantization errors and thus effective...

In communication systems the present trend is to move the border between the analog and digital interface as close as possible to the point where information is received or emitted, in this way most of SoC functionalities are implemented in the digital domain. in this work an efficient first order sigma delta modulator has been designed in circuit level, considering the possible non-idealities ...

DESIGN OF SECOND-ORDER SIGMA-DELTA MODULATOR USING CMOS TECHNOLOGY

In this paper, we propose and study an adaptive delta modulator that has improved SNR performance and better robustness in tracking highly varying signals. The step-size adaptation used in this modulator is based on information about the absolute value of the quantizer input. The modulator is shown to be free of zero-input limit cycles and is BIBO stable.

In previous work [ 11, we have proposed an adaptive sigma delta modulator with improved dynamic range. The modulator adapts the step-size of the quantizer from estimates of the quantizer input. In this paper, we conduct a stability analysis of the new modulator.

The paper proposes a novel structure for a MASH digital delta-sigma modulator (DDSM) in order to achieve a long sequence length. The expression for the sequence length is derived. The condition to produce the maximum sequence length is also stated. It is proved that the modulator output only depends on the structure of the first-order error feedback modulator (EFM1) which is the first stage of ...

A methodology for the design of Continuous-Time (CT) Sigma-Delta (Σ∆) modulators with VCO-based quantizer is proposed. The coefficients of the CT Σ∆ modulator are accurately calculated such that the noise transfer function of the modulator is exactly the same as a Discrete-Time (DT) Σ∆ modulator of the same order. Several design examples for different modulator orders and feedback DAC signal sh...

The design of single loop two-order Delta-Sigma modulator with feed forward structure is presented in this thesis. Oversampled analog-to-digital converters based on second-order delta-sigma modulation are attractive for VLSI implementation because they are especially tolerant of circuit nonidealities and component mismatch. The noise shaping and oversampling are used in this modulator, the over...

In a previous study [1], we proposed an adaptive sigma delta modulator with improved dynamic range. The modulator adapts the step size of the quantizer from estimates of the quantizer input instead of the modulator input. In this study, we conduct an error variance analysis of the new modulator and derive expression for the SNR. The derived expression shows that the SNR is independent of the in...