Device miniaturization is an important part of VLSI design, which refers to reduction in dimension of device by keeping all other characteristic constant. As technology node is moving in submicron region, the performance of the device degrades due to short channel effects and narrow channel effects. The key issues due to these effects are draininduced-barrier– lowering (DIBL), leakage current, ...

In this paper we study the feasibility of design/fabrication a vertical trench 4H-SiC Junction Field Effect Transistor (JFET), assuming realistic constraints depth P+ implantation. The doping profile is obtained using Monte Carlo implantation simulation. calculation used drift-diffusion approach. JFET aims to achieve threshold voltage of-3V. We found that constraint in concomitance with propose...

Abstract Reliability and controllability for a new scheme of gate-all-around field effect transistor (GAA-FET) with silicon channel utilizing sectorial cross section is evaluated in terms Ion/Ioff current ratio, transconductance, subthreshold slope, threshold voltage roll-off, drain induced barrier lowering (DIBL). In addition, the scaling behavior electronic figures merit comprehensively studi...

In the present work, Dual Material Gate (DMG) AlGaN/GaN High Electron Mobility Transistor (HEMT) has been studied for its improved linearity performance on the basis of VIP3 (i.e. extrapolated input voltage at which the first and third order harmonic voltages are equal) and compared with the conventional Single Material Gate (SMG) AlGaN/GaN HEMT. The influence of the device parameters such as t...

For the first time, a deep study of gate control coefficient (αG) effect on CNTFET performance has done in this research. A new, analytical CNTFET simulation along with multiple parameter approach has executed with 3D output in MATLAB and that used it to examine device performance. It is found that, drain current and transconductance increases with high gate control coefficient. On the other ha...

The novel characteristics of a new type of MOSFET, the hetero-material gate field-effect transistor (HMGFET), are explored theoretically and compared with those of the compatible MOSFET. Two conceptual processes for realizing the HMG structure are proposed for integration into the existing silicon technology. The two-dimensional (2-D) numerical simulations reveal that the HMGFET demonstrates ex...

In this work an attempt has been made to analyze the scaling limits of Double Gate (DG) underlap and Triple Gate (TG) overlap FinFET structure using 2D and 3D computer simulations respectively. To analyze the scaling limits of FinFET structure, simulations are performed using three variables: finthickness, fin-height and gate-length. From 2D simulation of DG FinFET, it is found that the gate-le...

In this paper, we propose a novel design analysis for a Junctionless Double Gate Vertical MOSFET (JLVMOS) with metal gate electrode and HfO2, for which the simulations have been performed using TCAD (ATLAS), The simulated results exhibits significant improvements in comparison to conventional JLVMOS device with a polysilicon gate electrode and ITRS values for different node technology . In plac...

A process of making a symmetrical self-aligned n-type vertical double-gate MOSFET (nVDGM) over a silicon pillar is revealed. This process utilizes the technique of oblique rotating ion implantation (ORI). The self-aligned region forms a sharp vertical channel profile and decreases the channel length Lg. A tremendous improvement in the drive-on current is noted. The electron concentration profil...