This paper describes the impression of low-k/high-k dielectric on performance Double Gate Junction less (DG-JL) MOSFET. An analytical model threshold voltage DG-JLFET has been presented. Poisson’s equation is solved using parabolic approximation to find out voltage. The effect high-k various parameters N-type explored. comparative analysis carried between conventional gate oxide, multi oxide an...

Abstract In this work, a hetero-gate-oxide charge plasma-based nanowire transistor (HGO-CPNWT) has been proposed, characterized, and comparative analysis with the conventional (CCPNWT) Stack-Gate-Oxide CPNWT (SGO-CPNWT) investigated. The effects of stacking high- κ gate oxide low- beneath segmenting at source side drain have analyzed short channel (SCEs) parameters radio-frequency (RF)/analog f...

In this work an attempt has been made to analyze the scaling limits of Double Gate (DG) underlap and Triple Gate (TG) overlap FinFET structure using 2D and 3D computer simulations respectively. To analyze the scaling limits of FinFET structure, simulations are performed using three variables: finthickness, fin-height and gate-length. From 2D simulation of DG FinFET, it is found that the gate-le...

Over the past 50 years of the semiconductor industry, the size of MOSFETs has been scaled down obeying the Moore’s law: feature sizes of transistors are scaled at a rate of approximately 0.7 times every 18 months. However, as CMOS technology approaches nanoscale region, researchers face with critical technology barrier known as short channel effect. While the gate voltage fully controls the cha...

In this paper electrical characteristics of various kinds of multiple-gate silicon nanowire transistors (SNWT) with the channel length equal to 7 nm are compared. A fully ballistic quantum mechanical transport approach based on NEGF was employed to analyses electrical characteristics of rectangular and cylindrical silicon nanowire transistors as well as a Double gate MOS FET. A double gate, tri...

Nanosheets are the revolutionary change to overcome limitations of FinFET. In this paper, temperature dependence 10 nm junctionless (JL) nanosheet FET performance on DC and analog/RF characteristics investigated for first time using extended source/drain with high-k gate stack. The detailed analysis like transfer (ID-VGS), output (ID-VDS), drain induced barrier lowering (DIBL), subthreshold swi...

In this article, the effects of non-ideal cross-sectional shapes stacked nanosheet FET (NSFET) and with inter-bridge channel (TreeFET) are studied through calibrated 3D TCAD simulations. The impact on electrical characteristics due to insufficient/excessive etch processes investigated in terms inner spacer (IS), (NS) channel, (IB) channel. Simulation results show that geometry material IS have ...

We investigated the source-to-drain capacitance (Csd) due to DIBL effect of silicon nanowire (SNW) MOSFETs. Short-channel SNW devices operating at high drain voltages have the positive value of Csd by DIBL effect. On the other hand, junctionless SNW MOSFETs without source/drain (S/D) PN junctions have negative or zero values by small DIBL effect. By considering the additional source-todrain cap...

Multi-gate MOSFETs has shown better results in subthreshold performances. The replacement of SiO2 by high-k dielectric can fulfill the requirements of Multi-gate MOSFETS with scaling trend in device dimensions. The advancement in fabrication technology has also boosted the use of different high K dielectric materials as oxide layer at different places in MOSFET structures. One of the most impor...

In this paper we present current voltage and trans-conductance model for Dual Material Gate AlGaN/GaN HEMT. Our proposed model demonstrates complete charge control in 2DEG based channel of the device in order to investigate the current-voltage as well as transfer characteristics of the device under various gate and drain biases. The proposed device structure uses GaN material capable to withsta...