Reza Sedaghat Maman Fault Emulation: Reconfigurable Hardware-Based Fault Simulation Using Logic Emulation Systems with Optimized Mapping Various approaches to test vector evaluation exist for ascertaining the effectiveness of a test vector set for a specific fault model by computing the ratio between the number of faults detected by this set and the number of modeled faults. The traditional app...

Reliability is one of the key problems of an automatic system, especially to the huge, complex, multiple target-based, safety critical and reliability-dependent train control system. A system reliability analysis method based on a dynamic fault tree was proposed to analyse possible fault causes of a whole system in a HLA (High Level Architecture) simulation platform, and according to the princi...

A fault simulator for large synchronous sequential circuits is presented in this paper. There are four key ideas to the fault simulator. 1) It uses the critical path tracing method to screen out the single event faults that need not map into equivalent stem faults. 2) It uses the single fault propagation method to map the traced single event faults into equivalent stem faults. 3) All the multip...

Faults injection attacks have become a hot topic in the domain of smartcards. This work exposes a source code-base simulation approach designed to evaluate the robustness of high-level secured implementations against single and multiple fault injections. In addition to an unprotected CRT-RSA implementation, we successfully attacked two countermeasures with the high-level simulation under the da...

in this paper, the fuzzy system has been used for fault detection and diagnosis of a yeast fermentation bioreactor based on measurements corrupted by noise. in one case, parameters of membership functions are selected in a conventional manner. in another case, using certainty factors between normal and faulty conditions the optimal values of these parameters have been obtained through the genet...

A silicon independent C-Based model of the TTP/C protocol was implemented within the EU-founded project FIT. The C-based model is integrated in the C-Sim simulation environment. The main objective of this work is to verify whether the simulation model of the TTP/C protocol behaves in the presence of faults in the same way as the existing hardware prototype implementation. Thus, the experimental...

The system fault behavior model was investigated by the author first. System fault behavior model describes the occurrence and development process of malfunction in product, and analyzes the transmission process of unit malfunction in system and effects of various factors on system. In order to realize simulation of system fault behavior, it is necessary to perform formalized process of system ...

This paper describes a technique to accelerate diagnostic fault simulation of sequential circuits using fault sampling. Diagnostic fault simulation involves computing the indistinguishability relationship between all pairs of modeled faults. The input space is the set of all pairs of modeled faults, thus making the simulation computationally intensive. The diagnostic simulation process is accel...

We present an approach to hierarchical fault simulation which generates several simulation-models of one circuit and carries out simulation for each. Fault insertion and simulation-model generation is done automatically. Switch-level simulation which utilizes look-up tables is as fast as gate-level simulation. Experimental results show that using behavioral description and switch-level truth ta...