نتایج جستجو برای: field programmable gate array fpga implementation
تعداد نتایج: 1254713 فیلتر نتایج به سال:
In this paper, an Ultra High Frequency (UHF) base band processor for a passive tag is presented. It proposes a Radio Frequency Identification (RFID) tag digital base band architecture which is compatible with the EPC C C2/ISO18000-6B protocol. Several design approaches such as clock gating technique, clock strobe design and clock management are used. In order to reduce the area Decimal Matrix C...
This paper proposes a parallel fixed point radial basis function (RBF) artificial neural network (ANN), implemented in a field programmable gate array (FPGA) trained online with a least mean square (LMS) algorithm. The processing time and occupied area were analyzed for various fixed point formats. The problems of precision of the ANN response for nonlinear classification using the XOR gate and...
Truncated multiplier is a good candidate for digital signal processing (DSP) applications including finite impulse response (FIR) and discrete cosine transform (DCT). Through truncated multiplier a significant reduction in Field Programmable Gate Array (FPGA) resources can be achieved. This paper presents for the first time a comparison of resource utilization of Spartan-3AN and Virtex-5 implem...
In this paper, we argue that the utilization of field-programmable gate array (FPGA) structures can improve the performance of embedded systems based on programmable processor cores. Furthermore, in multimedia processing it is well-known that the sum-of-absolutedifferences (SAD) operation is the most time-consuming operation when implemented in software running on such programmable processor co...
This paper deals with the implementation of PID controller for a DC motor controller application on FPGA platform. The soft IP core of PID controller is implemented on FPGA ALTERA Quartus II platform by using Quartus II software version 10.1. The PWM signal is generated by ALTERA board, which further given to DC motor for its speed control. The soft IP core of PID controller is prototyped and v...
Halftoning is a fairly slow process when executed by software on conventional processors. To speed up halftoning, a halftoning algorithm has been developed and integrated into a dedicated hardware architecture. This paper describes the implementation of the architecture with a XILINX Field Programmable Gate Array (FPGA) and compares its performances with results obtained by a software implement...
This paper addresses efficient hardware/software implementation approaches for the AES (Advanced Encryption Standard) algorithm and describes the design and performance testing algorithm for embedded system. Also, with the spread of reconfigurable hardware such as FPGAs (Field Programmable Gate Array) embedded cryptographic hardware became cost-effective. Nevertheless, it is worthy to note that...
Electronic design tools and techniques for the implementation of a stereoscopic camera based on an FPGA (Field Programmable Gate Array) are presented. The stages of an IPP (Image Processing Pipeline) are presented together with the development tools and languages used to implement a stereoscopic camera in hardware. In a further development of the basic system, aspects of the implementation of a...
Multiple-input-multiple-output (MIMO) technique is often employed to increase capacity in comparing to systems with single antenna. However, the computational complexity in evaluating channel capacity or transmission rate (data rate) grows proportionally to the number of employed antennas at both ends of the wireless link. Recently, the QR decomposition (QRD) based detection schemes have emerge...
نمودار تعداد نتایج جستجو در هر سال
با کلیک روی نمودار نتایج را به سال انتشار فیلتر کنید