The choice of flip-flop technologies is an essential importance in design of VLSI integrated circuits for high speed and high performance CMOS circuits. The main objective of this project is to design a Low-Power Pulse-Triggered flip-flop. Flip-flops are the major storage elements in all SOC’s of digital design. They accommodate most of the power that has been applied to the chip. Flip-flop is ...

We construct natural equivalences between derived categories of coherent sheaves on the local models for stratified Mukai or Atiyah flops (of type A).

Existing Hierarchically Semi-Separable (HSS) construction algorithms for dense n×n matrices require as much as O(n2) peak workspace memory, at a cost of O(n2) flops. An algorithm is presented which requires O(n1.5) peak worskpace memory in the worst case, while still requiring only O(n2) flops.

In this paper a detailed analysis for how the number of flip-flops and latches inserted are effecting BER and repeater size with wire pipelining is performed. Since number of flip-flops, latches and repeater sizes cannot scaled down beyond a certain limit due to the solidity requirement, which is determined by maximum allowable bit error rate.

described. A new clock is developed according to which circuit makes transition as well as retains present, past & former past information. The proposed flip-flops are constructed using clocked T-Gates that reduces the number of transistors required to implement single clocked gates. In the verification by simulation, the proposed flip-flops appear to have lesser power consumption, better speed...

All practical digital circuits are usually a mixture of combinational and sequential logic. Flip–flops are essential to sequential logic therefore fuzzy flip–flops are considered to be among the most essential topics of fuzzy digital circuit. The concept of fuzzy digital circuit is among the most interesting applications of fuzzy sets and logic due to the fact that if there has to be an ultimat...

In this paper, we examine the problems in the CDN of the flip flop & design an improved CDN oriented Flip-flop which is Clocked Pair Shared Flip Flop (CPSFF). Clock Division Network (CDN)’S plays an important role in the flip flop design and it’s the major element in the flip –flop for producing the logical outputs it’s much important to design the CDN with low power and area. Power consumption...

The consumption of power has become an important issue in modern VLSI design. Power consumption can be reduced by replacing some flip-flops with fewer multi-bit flip-flops. Multi-bit flip-flop is one of the methods for clock power consumption reduction. This project focuses on reduction of power using multi-bit flipflops by clock synchronization. Two single bit flip-flops are synchronized with ...

Frequency synthesizer is one of the important element for wireless communication application. The speed of VCO and prescaler determines how fast the frequency synthesizer is. A dual modulus prescaler contains logic gates and flip-flops. To fulfill the need of high frequency and low voltage circuit suitable flipflops must be selected. Four different classes of flip-flops like master-slave, pulse...

Power consumption of the clock tree dominates over 40% of the total power in modern high performance VLSI designs, measures must be taken to keep it under control. Hence, low power clocking schemes are promising approaches for low-power design. We propose four novel energy recovery clocked flip-flops that enable energy recovery from the clock network, resulting in significant energy savings. Th...