Mixed-signal AI accelerators offer the possibility of higher energy efficiency for moderate resolution computations compared to their digital counterparts. All-analog implementations, where all operations are performed in analog domain, can further improve this advantage. An efficient multiply-accumulate cell all-analog neural layer processing macros is presented. The proposed two-quadrant mult...

A new architecture of simple low voltage BiCMOS fourquadrant multiplier is proposed and analyzed. It operates with ±1.5V power supplies and 3Vp-p fully input signal swings. Simulation results based on AMS 0.8μm n-well BiCMOS process parameters are given to verify the theoretical analysis. The architecture of four multipliers typically have a nonlinearity error less than 1% over ±1.5V input rang...

A novel CMOS monolithic analog multiplier capable of operating in two quadrants is described in this thesis. The multiplier incorporates a voltage-controlled variable linear resistor comprised of two FET transistors in the feedback network of an operational amplifier. This novel approach to implementing an analog multiplier results in good linearity and wide input dynamic range when compared to...

This work presents a four-quadrant current-mode CMOS multiplier structure based on the Advanced Compact MOSFET (ACM) Model. On the contrary of most traditional approaches for implementing CMOS multipliers, the proposed configuration is valid in the whole inversion regime of the MOS transistor, providing wide input range and improved linearity. The main theoretical principle of our multiplier li...

Real-time analog multiplication of two signals is one of the most important operations in analog signal processing. The multiplier is used not only as a computational building block but also as a programming element in systems such as filters, neural networks, and as mixers and modulators in a communication system. Although high performance bipolar junction transistor multipliers have been avai...

This paper presents a low-voltage, low-power and faulttolerant implementation of Double Sideband Suppressed Carrier (DSB-SC) amplitude modulator-demodulator circuit for portable communication systems. Through the approximation proposed in this work, a CMOS four quadrant multiplier is used as a (de)modulator circuit to generate DSB-SC (de)modulated signals. Furthermore, the proposed fault-tolera...