Although verification and simulation tools are always improving, the results they provide remain hard to analyze and interpret. On one hand, verification sticks to the functional description of the circuit, with no timing consideration. On the other hand, simulation runs mainly on subsets of the entire input domain. Furthermore, these tools provide results in a format (e.g. state graphs, bit ve...

We present an 8-bit field programmable gate arr (FPGA) implementation of 128-bit block and 128-bit k Advanced Encryption Standard (AES) Rijndael. The 8Rijndael encryption data path operates at 13.7MHz a consumes 226 clock cycles resulting in a throughput of 7.8 bits per second. The Rijndael decryption data path operates 8.8MHz and consumes 226 clock cycles resulting in throughput of 5 M bits pe...

Field-Programmable Gate Arrays have become popular ever since their introduction. Compared to other digital circuit implementation media, they have lower NRE cost and rapid turnaround with the penalties of reduced speed and larger size. Thus better FPGA programmable switch technology is desired in order to gain speed and density advantages. In this paper, Laser-induced MakeLink technology is pr...

The field programmable gate array is the fastest growing technology. The bio-impedance measurement system is implemented in reconfigurable field programmable gate array hardware. The design of bio-impedance measurement system using Xilinx system generator is more convenient and cheaper for revising, if the Bio-impedance measurement system requires parameters changes in practical use, since no n...

We show how, given any set of generators of the stabilizer of a quantum code, an efficient gate array that computes the codewords can be constructed. For an n-qubit code whose stabilizer has d generators, the resulting gate array consists of O(nd) operations, and converts k-qubit data (where k = n − d) into n-qubit codewords. 02.70.Rw, 03.65.Bz, 89.80.+h Typeset using REVTEX ∗[email protected]...

This paper presents an innovative architecture for a reconfigurable device that allows single cycle context switching and single cycle random access to the unified on-chip configuration/data memory. These two features are necessary for efficient self-reconfiguration and are useful in general as well—no other device offers both features. The enhanced context switching feature permits arbitrary r...

A monolithically integrated ISFET sensor array and interface circuit are described. A new high-density, low-power source-drain follower was developed for the sensor array. ISFETs were formed by depositing Au/Ti extended-gate electrodes on standard MOSFETs, then thin silicon nitride layers using catalytic chemical vapor deposition and/or SU-8 protective layers were formed on the extended-gate el...

Flexible transistor active matrix array is fabricated on PEN substrate using all screen-printed gate, source and drain electrodes. Parylene-C and DNTT act as gate dielectric layer and semiconductor, respectively. The transistor possesses high mobility (0.33 cm 2 V -1 s -1 ), large on/off ratio (> 10 6 ) and low leakage current (~10 pA). Active matrix array consists of 10×10 transistors were dem...

This paper introduces the Field-Programmable Learning Array, a new paradigm for rapid prototyping of learning primitives and machinelearning algorithms in silicon. The FPLA is a mixed-signal counterpart to the all-digital Field-Programmable Gate Array in that it enables rapid prototyping of algorithms in hardware. Unlike the FPGA, the FPLA is targeted directly for machine learning by providing ...