This work presents a comparative study of the transcapacitances an asymmetric self-cascode (A-SC) and graded-channel (GC) silicon-on-insulator (SOI) nMOSFETs with different gate lengths. analysis was done by means two-dimensional numerical simulations. Simulated results show influence others on gate-to-gate capacitance for ASC SOI device GC device.

We discuss the effect of dielectric environment (substrate/bottom oxide, gate insulator, and metal gates) on electronic transport in two-dimensional (2D) transition dichalcogenides (TMD) monolayers. employ well-known ab initio methods to calculate low-field carrier mobility free-standing layers use continuum approximation extend our study double-gate structures, including effects screening elec...

We have studied electron mobility behavior in asymmetric double-gate silicon on insulator ~DGSOI! inversion layers, and compared it to the mobility in symmetric double-gate silicon on insulator devices, where volume inversion has previously been shown to play a very important role, being responsible for the enhancement of the electron mobility. Poisson’s and Schroedinger’s equations have been s...

Double gate MOSFET is widely used for sub-50nm technology of transistor design .They have immunity to short channel effects, reduced leakage current and high scaling potential. The single gate Silicon–on-insulator (SOI) devices give improved circuit speed and power consumption .But as the transistor size is reduced the close proximity between source and drain reduces the ability of the gate ele...

In this article we give an overview over the physical mechanisms involved in the electronic transport in ultrathinbody SOI Schottky-barrier MOSFETs. A strong impact of the SOI and gate oxide thickness on the transistor characteristics is found and explained using experimental as well as simulated data. We elaborate on the influence of scattering in the channel and show that for a significant ba...

This paper analyzes in detail the Fringing Induced Barrier Lowering (FIBL) in MOS transistors with high-K gate dielectrics using two-dimensional device simulations. We found that the device short channel performance is degraded with increase in gate dielectric permittivity(Kgate) due to an increase in the dielectric physical thickness to channel length ratio. For Kgate greater than Ksi, we obse...