In this paper a new approach is introduced for implementing the basic logic functions using analog current-mode techniques. By expanding the logic functions in power series expressions, and using summers and multipliers, realization of the basic logic functions is simplified. To illustrate the proposed technique, a CMOS circuit for simultaneous realization of the logic functions NOT, OR, NAND a...

In this paper we propose new three-input XOR and three-input XNOR gate based on generalized threshold gate (GTG) topology. The GTG topology is main part is monostable-bistable logic element (MOBILE). The proposed gates use fewer elements count in comparison with other implementations which utilize MOBILE as a main structure. By exploiting the new three-input XOR gate and a carry generator, we p...

Four di erent CMOS inverter delay models are derived and compared. It is shown that inverter delay can be estimated with fair accuracy over a wide range of input rise times and loads as the sum of two terms, one proportional to the input rise time, and one proportional to the capacitive load. Methods for estimating device capacitance from HSPICE parameters are presented, as well as means of inc...

This communication presents the evidence of a degradation effect causing important reductions in the delay of a CMOS inverter when consecutive input transition are close in time. Complete understanding of the effect is demonstrated, providing a quantifying model. Fully characterization as a function of design variables and external conditions is carried out, making the model suitable for using ...

G4-FET has attracted attention as an emerging device for the future generations of semiconductor industry. This paper is intended to propose a model representing the characteristics of G4FET device in order to perform circuit simulations. The modeling approach is established upon the neuro-fuzzy technique whose main strength is that they are universal approximators with the ability to solicit i...

Abstract: In this paper we present a simple ultra low-voltage and high speed D flip-flop. The delay of the static differential flip-flop presented is less than 12% compared to conventional differential CMOS flip-flops. The presented circuits have been simulated using Hspice and are valid for 90nm TSMC CMOS process. The proposed high-speed and ultra low-voltage flip-flop can be used for any digi...

This paper reports a multitude of HSPICE simulation results corresponding to high-order (fifth, sixth and tenth) differential classA log-domain lowpass and bandpass ladder filter topologies. The designs are elliptically approximated and were obtained by means of an appropriately extended version of the XFILTER filter compiler. The non-desirable effect of the BJT finite beta is shown; circuit mo...

A CMOS frequency-insensitive quadrature phase shifter is presented. Due to operation in current-mode, the proposed circuit provides a wide frequency response, a low supply voltage, low power consumption and electronic controllability. Thus, it is very suitable for use in portable and battery-powered equipments. The feature of the proposed circuit is that it can provide the quadrature signals wi...

One-dimensional (1-D) Dynamic supply Voltage Scaling (DVS) scheme with image distortion compensation is proposed for reducing the static power consumption in AMOLED displays. A hybrid simulation platform combining MATLAB and circuit simulator HSPICE was built for the study. By applying the DVS scheme to both static images and video streams, it is shown significant power saving can be achieved (...

A new CMOS buffer without short-circuit power consumption is proposed. The gatedriving signal of the output pull-up (pull-down) transistor is fed back to the output pull-down (pull-up) transistor to get tri-state output momentarily, eliminating the short-circuit power consumption. The HSPICE simulation results verified the operation of the proposed buffer and showed the power-delay product is a...