This paper examines the impact of two important geometrical parameters, namely the thickness and source/drain extensions on the performance of low doped p-type double lateral gate junctionless transistors (DGJLTs). The three dimensional Technology Computer-Aided Design simulation is implemented to calculate the characteristics of the devices with different thickness and source/drain extension a...

In this paper, a silicon-oxide-nitride-silicon nonvolatile memory constructed on an n+-poly-Si nanowire [NW] structure featuring a junctionless [JL] configuration is presented. The JL structure is fulfilled by employing only one in situ heavily phosphorous-doped poly-Si layer to simultaneously serve as source/drain regions and NW channels, thus greatly simplifying the manufacturing process and ...

The high temperature dependence of junctionless (JL) gate-all-around (GAA) poly-Si thin-film transistors (TFTs) with 2-nm-thick nanosheet channel is compared with that of JL planar TFTs. The variation of SS with temperature for JL GAA TFTs is close to the theoretical value (0.2 mV/dec/K), owing to the oxidation process to form a 2-nm-thick channel. The bandgap of 1.35 eV in JL GAA TFTs by fitti...

A comparative study of the drain breakdown phenomena in junctionless (JL) and inversion mode (IM) pchannel MOSFETs has been investigated experimentally with different VGS, channel widths, and VSUB. In order to explain the dependence of drain breakdown voltages (BVDS) on VGS, 3-D device simulation has been also performed. When the device is turned ON, the BVDS is larger in JL than IM transistors...

This work presents new insights into 3D logic circuit design with vertical junctionless nanowire FETs (VNWFET) accounting for underlying electrothermal phenomena. Aided by the understanding of nanoscale heat-transport in VNWFETs through multiphysics simulations, SPICE-compatible compact model captures temperature and trapping effects principally a shift device threshold voltage. Circuit level s...