This paper presents a new ?-Ga2O3 Junctionless double gate Metal-Oxide-Field-Semiconductor-Effect-Transistor (?DG-JL-FET) with an embedded P+ packet at the oxide layer (PO-?DG-JL-FET) for high-frequency applications. Our goal is to achieve efficient volume depletion region by placing of silicon. We show that proposed structure has subthreshold swing ? 64 mV/decade. It suppressed band-to-band tu...

In this paper, we propose a new heterostructure dual material gate junctionless field-effect transistor (H-DMG-JLFET), with negative differential resistance (NDR) characteristic. The drain and channel material are silicon and source material is germanium. The gate electrode near the source is larger. A dual gate material technique is used to achieve upward band bending in order to access n-i-p-...

In this paper, a Junctionless Accumulation Mode Ferroelectric Field Effect Transistor (JAM-FE-FET) has been proposed and assessed in terms of RF/analog specifications for varied channel lengths through simulations using TCAD Silvaco ATLAS simulator, the Shockley-Read-Hall (SRH) recombination, ferro, Lombardi CVT, fermi LK models. Major analog metrics like transconductance (gm), intrinsic gain (...

This study discusses the use of a triple material gate (TMG) junctionless tunnel field-effect transistor (JLTFET) as biosensor to identify different protein molecules. Among plethora existing types biosensors, FET/TFET-based devices are fully compatible with conventional integrated circuits. JLTFETs preferred over TFETs and JLFETs because their ease fabrication superior biosensing performance. ...

In this paper, an 18nm dopingless asymmetrical junctionless (AJ) double gate (DG) MOSFET has been designed for suppressed short channel effects (SCEs) low power applications. A desired ON and OFF state current ratio with subthreshold performance parameters under limit, is the major focus of proposed transistor. Different sensitivity AJ DG such as drain extension, length overlapping oxide thickn...

Planar MOS devices miniaturization becomes quite challenging for transistors with reduced channel length due to the loss of gate control over the channel charges. As an alternative, multi-gate devices have been developed due to the better electrostatic control of the charges, which leads to a reduction of the short-channel effects [1-6]. However, for devices with extremely reduced channel lengt...