In this paper, electric field distribution of the junctionless dual material surrounding gate MOSFETs (JLDMSG) is developed. Junctionless is a device that has similar characteristics like junction based devices, but junctionless has a positive flatband voltage with zero electric field. In Surrounding gate MOSFETs gate material surrounds the channel in all direction , therefore it can overcome t...

In this paper, we proposed a 2-D analytical model for electrical characteristics such as surface potential, electric field and drain current of Silicon-on-Insulator Tunnel Field Effect Transistor (SOI TFETs) with a SiO2/High-k stacked gate-oxide structure. By using superposition principle with suitable boundary conditions, the Poisson’s equation has been solved to model the channel r...

A Hetero Dielectric Tunnel field effect transistor with the spacer on both sides of gate is proposed in this paper. The performance and characteristics using ATLAS Technology Computer-Aided Design 5nm regime were analyzed. band-to-band tunneling leakage current will be reduced by introducing heterojunction hetero dielectric material structure. In transistor, double metal high-k improves high su...

To sustain transistor scaling beyond lateral 7 nm devices, gate-all-around (GAA) junctionless vertical nanowire field effect transistors (JLNT) are one of the promising alternatives. overcome roadblocks logic cell design using this emerging technology, work explores compact modeling 3D GAA-JLNTs based on physics transport. The model features an explicit continuous analytical form drain current ...