The spectrum ω(G) of a finite group G is the set of element orders of G. If Ω is a non-empty subset of the set of natural numbers, h(Ω) stands for the number of isomorphism classes of finite groups G with ω(G) = Ω and put h(G) = h(ω(G)). We say that G is recognizable (by spectrum ω(G)) if h(G) = 1. The group G is almost recognizable (resp. nonrecognizable) if 1 < h(G) < ∞ (resp. h(G) = ∞). In t...

In this paper I will show that it is relatively consistent with the usual axioms of mathematics (ZFC) together with a strong form of the axiom of infinity (the existence of a supercompact cardinal) that the class of uncountable linear orders has a five element basis. In fact such a basis follows from the Proper Forcing Axiom, a strong form of the Baire Category Theorem. The elements are X , ω1,...

There are several graphs associated with finite groups which are currently of interest in the field. This subject of this project are graphs related to the element orders of a finite group. The best known such graph is the prime graph Γ(G) of the group G and is defined as follows. The vertices are the prime numbers dividing the order (=number of elements) of the group, and two such primes are l...

Well-founded orders are the opposite of noetherian orders: every nonempty subset contains at least one minimal element. And a set is well-ordered when it is totally ordered by a wellfounded order: every nonempty set contains exactly one minimal element. Sofar, noetherian induction has been the most powerful way of proving properties inductively; it is indeed the most general one in the precise ...

The notation "" for OR is bad and misleading. Just think that in the context of boolean functions, the author uses  instead of ∨.The integers modulo 2, that is Z2  0,1, have an addition where 1  1  0 while 1 ∨ 1  1. A set A is partially ordered by a binary relation ≤, if this relation is reflexive, that is a ≤ a holds for every element a ∈ S, it is transitive, that is if a ≤ b and b ≤ c...

To truly exploit FPGAs for rapid turn-around development and prototyping, placement times must be reduced to seconds; latebound, reconfigurable computing applications may demand placement times as short as microseconds. In this paper, we show how a systolic structure can accelerate placement by assigning one processing element to each possible location for an FPGA LUT from a design netlist. We ...