The phase-locked loop (PLL) propagation time is important unavoidable factor for high-speed coherent detection systems using broad-linewidth laser diodes. This paper report the linewidths requirements and the power penalties taking into account the loop propagation delay. The coherent optical receivers with PLL, based on Costas loop or decision driven loop (DDL) are taken into consideration. Th...

Grid connected applications require an accurate estimate of the grid angle to feed power synchronously to the grid. This is achieved using a software phase locked loop (PLL). This application report discusses different challenges in the design of software phase locked loops and presents a methodology to design phase locked loops using C2000 controllers for single phase grid connection applicati...

In this paper a new method is proposed that can be used to differentiate faults from switching transients. The method is primarily intended for use in systems where fast fault detection and fast fault clearing before the first peak of the fault current are required. An industrial system, in which high short-circuit power is desired but in which high shortcircuit currents cannot be tolerated is ...

A fully integrated phase-locked loop (PLL) fabricated in a 0.24 micrometer, 2.5v digital CMOS technology is described. The PLL is intended for use in multi-gigabit-per-second clock recovery circuits in fiber-optic communication chip. This PLL first time achieved a very large locking range measured to be from 30MHz up to 2GHz in 0.24 micrometer CMOS technology. Also it has very low peak-to-peak ...

This paper presents a novel Phase frequency detector for Charge Pump Phase locked loop (PLL) applications to enable fast frequency acquisition in the phaselocked loop (PLL). To cope with the missing edge problem, the proposed PFD predicts the reset signal and blocks the corresponding input signal during the reset time. The blocked edge is regenerated after the reset signal is deactivated [1]. T...

Phase-locked loop (PLL) frequency synthesizers used for high-speed data transmission must rapidly hop and lock to new frequencies. The fundamental problem is that the settling time depends inversely on the loop bandwidth, and increasing the bandwidth causes unwanted noise interference and stability problems for the circuit. We demonstrate the feasibility of replacing the analog integrator in th...

We present a fully integrated Phase Locked Loop in an advanced 45nm CMOS technology. The loop filter is integrated on chip under the voltage-controlled oscillator inductor, resulting in significant area savings. The whole PLL measures only 280um by 150um. The PLL has a dual-band output for 2-2.5GHz and 4-5GHz. The circuit operates from a 0.85V supply and consumes 15.3mW for a -120dBc/Hz phase n...

V m f 4 AbstractA phase-locked loop (PLL) frequency synthesizer architecture for multiple-band applications is presented. A dynamically-controlled switched tuning voltage-controlled oscillator (VCO) is used to achieve superior frequency range and phase noise performance over a conventional PLL. . Implemented in 1 .w CMOS, the PLL has a 111-29OMHz range, phase noise of -92.3dBdHz at a 5OkHz offs...

In this paper, an integral-type half-tangent phase-locked loop (IHTan-PLL) is proposed for the varying-frequency AC grids of more electric aircraft (MEA). First, performance synchronous reference frame (SRF-PLL) and (HTan-PLL) discussed from a large-signal viewpoint. When frequency changes largely, SRF-PLL has many oscillations endures rather long transient process. The HTan-PLL can address lar...

This work aims at analyzing three different techniques for synchronizing RF oscillators. These techniques are Injection Locking (ILO), Phase Locked Loop (PLL) and Injection Locked Phase Locked Loop (ILPLL). ILPLL, which is a combination of PLL and ILO, has superior noise performance –compared to all the restat medium frequency offsets and the same noise performance at low and high offsets. Furt...