We propose an analog current-mode subthreshold CMOS circuit implementing a piecewise linear neuromorphic oscillator. Our circuit was derived from a piecewise linear oscillator model proposed by Matsuoka, well known as a building block for constructing a robot locomotion controller. We modified Matsuoka’s oscillator to be suitable for analog current-mode integrated circuit implementation, and de...

In this paper we present a new transistor sizing methodology called Free Power Recovery (FPR) for low power circuit design. The objective of this methodology is to minimize the total power of a circuit by accounting for node switching activities and leakage duty cycles (LDC). The methodology has been incorporated into the EinsTuner circuit tuning tool. EinsTuner automates the tuning process usi...

The continuous scaling down of technology, there is the exponential increase in leakage current. The MTCMOS is an attractive design to reduce the leakage current in idle state. Sleep-to-Active mode transition is an important concern in MTCMOS circuit because it produces ground bounce noise. In this paper, Threshold Voltage tuning method with MTCMOS circuit is used to reduce the ground bounce no...

This paper presents a new realization of resistorless mixed-mode (i.e. both voltage-mode and currentmode) quadrature sinusoidal oscillator using a new active building block (ABB) called the differential voltage current-controlled conveyor transconductance amplifier (DVCCCTA). The proposed oscillator circuit uses a single DVCCCTA, two grounded capacitors (GCs) and does not employ any external li...

In this paper, we propose a five-transistor (5T) static random access memory (SRAM) that can be read and written reliably with the assistance of read/write circuits. The read/write circuits include a voltage control circuit, a pre-charging circuit and a standby start-up circuit. The voltage control circuit is connected to the sources corresponding to driver transistors of each row memory cells....

The design and simulation of Winner-Take –All Current Mode (WTA) circuit is proposed. The proposed novel current mode CMOS WTA operates at 0.7v, which makes the circuit appropriated for low voltage hardware computation. The circuit was designed and simulated using Cadence gpdk090, with resolution of 0.001fA and an input dynamic range 50nA-10fA and power dissipation during competition is of arou...

This paper presents a CMOS current-mode S-shape correction circuit. The S-shape correction function is proposed to suit for panel-to-panel LCD displays by selecting a fractional value. Simulated results are at 1.8V supply voltage for 0.35μm CMOS process. Image quality improvement due to S-shape correction is observed. The -3dB bandwidth are about 50 MHz for the proposed circuit. Key-Words: LCD,...

A current-mode squarer/divider circuit with a novel translinear cell is presented for automotive applications. The proposed circuit technique increases the accuracy of the squarer/divider function with better input dynamic range and temperature insensitivity. Simulation results show that the variation of the output current is within ±0.2% over the temperature range from −40◦C to 140◦C. key word...

A CMOS continuous time current-mode circuit which provides the maximum of n analog inputs is presented. This structure exhibits a O(n) complexity, and allows high precision and speed with small area and very low power dissipation. Its operation is discussed and illustrated with simulation results. INTRODUCTION Multiple-input Max/Min circuits are basic building blocks in many advanced computatio...

Combination of A/D-D/A converters allows implementing multiplier/divider operations. An efficient design based on continuous-time, current-mode, dividing-algorithmic converters is presented in this paper. It offers high speed and capability of low voltage operation, and it is suitable for applications of low or middle resolution (below 9 bits). In addition, the division result is given in both ...