This paper presents a mathematical analysis of the ripple voltage caused by a mismatch in parasitic capacitances in multi-phase, clocked charge pumps. Through detailed circuit modeling, we show that a relatively large pedestal ripple is caused by a small mismatch in parasitic capacitance. We present a simple circuit solution and verify its performance with simulation and experimental results.

Synchronous buck converters generate broadband noise typically in 50 – 300 MHz range due to the parasitic LC resonance in the switching loop which consists of input decoupling capacitors, high-side MOSFET and low-side MOSFET. Typically, this parasitic resonance is attenuated using an R-C snubber placed parallel to the low-side MOSFET. However, selection of the R and C value of the snubber is no...

This paper examines the recently introduced chargebased capacitance measurement (CBCM) technique through use of a three-dimensional (3-D) interconnect simulator. This method can be used in conjunction with simulation at early process development stages to provide designers with accurate parasitic interconnect capacitances. Metal to substrate, interwire, and interlayer capacitances are each disc...

Due to higher power and faster switching frequencies a very robust power distribution network is required. To achieve this the power distribution network needs to be modeled accurately at different stages of the design cycle. We present a methodology for the design and analysis of power distribution networks. The methodology covers the need for power grid analysis across all stages of the desig...

Received April 27, 2012 Revised May 14, 2012 Accepted May 26, 2012 Application of symmetric double gate vertical metal oxide semiconductor field effect transistors (MOSFETs) is hindered by the parasitic overlap capacitance associated with their layout, which is considerably larger than for a lateral MOSFET on the same technology node. A simple process simulation has been developed to reduce the...

Power module design is needed for high system performance and reliability, especially in terms of high efficiency and high power density. Low parasitic impedance and thermal management is desired for the lower power loss and device stress. For power module with high efficiency and improved breakdown voltage, this thesis proposes a novel series-connected power MOSFETs module. Three IRF7832 MOSFE...

iii Summary This master thesis describes the development of a new type RF PA and upconverter combination. Instead of the normally used voltage steering the amplifier uses charge steering. The parasitic capacitances of the MOSFET in combination with using charge steering form a feedback network that linearizes the amplifier. The developed device is a switching amplifier. For good behavior it use...

Parasitic capacitances of Proton Exchange Membrane (PEM) fuel cell are causing electrical effects resulting with change of dynamic behavior of fuel cell stack output voltage. This paper shows PEM fuel cell dynamic model with capability of easy integration of humidity, temperature and pressures dynamics, as well as their control. Fuel cell stack dynamic model was linked with boost converter aver...

Power dissipation of very large scale integrated circuits (VLSI) has emerged as a significant constraint on the semiconductor industry. For the dynamic power the voltage, capacitance and frequency are the major components of the power dissipation. In this paper, we propose a new power macromodeling technique for the power estimation of conventional metal-oxidesemiconductor (MOS) transistors. As...

We aim at constructing a common platform for compact model development based on the Verilog-A language for collaboration among different research groups. The project aims in particular at a framework for efficient development of multi-gate MOSFET models for circuit simulation. We have developed several prototypes of multi-gate MOSFET models based on different concepts till now. Phenomena expect...