Novel topological measures for static multiprocessor interconnection networks, disconnectivity, looseness', and cost-effectiveness, are developed. These and other measures are employed for a comparative analysis of such networks. The goal of this analysis is to predict network effectiveness, without resorting to execution benchmark techniques. In particular, we compare the hypereube and perfect...

A reconfigurable interconnection network based on a multi-ring architecture called REFINE is described. REFINE embeds a single l-factor of the Boolean hypercube in any given configuration. The mathematical properties of the REFINE topology and the hardware for the reconfiguration switch are described. The REFINE topology is scalable in the sense that the number of interprocessor communication l...

Let D be the diameter of a graph G and let λ1 be the largest eigenvalue of its (0,1)adjacency matrix. We give a proof of the fact that there are exactly 69 non-trivial connected graphs with (D + 1)λ1 9. These 69 graphs all have up to 10 vertices and were recently found to be suitable models for small multiprocessor interconnection networks. We also examine the suitability of integral graphs to ...

We study the cross product as a method for generating and analyzing interconnection network topologies for multiprocessor systems. Consider two interconnection graphs G1 and G2 each with some established properties such as symmetry, low degree and diameter, scalability, simple optimal routing, recursive structure (partitionability), fault tolerance, existence of nodedisjoint paths, low cost emb...

Multistage interconnection network has been very frequently proposed as connection means in classical on-board multiprocessor systems, it promises to be the solution for the interconnection problems. This paper tries to adapt such networks for embedded system design. Our approach is to analyze the dynamicity of the link permutation of Delta MINs for MPSOC architectures. This paper presents the ...

Design and implementation of a free-space optical backplane for multiprocessor applications is presented. The system is designed to interconnect four multiprocessor nodes that communicate by using multiplexed 32-bit packets. Each multiprocessor node is electrically connected to an optoelectronic VLSI chip which implements the hyperplane interconnection architecture. The chips each contain 256 o...

Many multiprocessor systems have interconnection networks as underlying topologies and an interconnection network is usually represented by a graph where nodes represent processors and links represent communication links between processors. In 2016, Zhang et al. proposed the g-extra diagnosability of G, which restrains that every component of G − S has at least (g + 1) vertices. As an important...

In the near future, interconnection networks of massively parallel computer systems will connect more than a hundred thousands of computing nodes. The performance evaluation of the interconnection networks can provide real insights to help the development of efficient communication library. Hence, to evaluate the performance of such interconnection networks, simulation tools capable of modeling...

We present a design of a scalable interconnection network that possesses a hierarchical structure. We also present the network topology, features, and performance analysis. The proposed network is well suited to optical implementation and will be used in massively parallel systems. This network is called a SCalable OPtical Interconnection Network (SCOPIN). SCOPIN is a single-hop, scalable, flex...

This paper introduces a new approach for a network on chip (NOC) design which is based on a NlogN interconnect topology. The intended application area for the NOC is the real-time communication of multiprocessors that are hosted by a single Field Programmable Gate Array (FPGA). The proposed NOC is an on-chip multistage interconnection network for which an upper limit can be guaranteed that is a...