The Network-on-Chip architecture and design methodology aims at providing a communication backbone for on-chip communication which can cope with the complexity of future System-on-Chip designs. Given the high number of resources and applications in a NoC, different communication streams will have different Quality-of-Service requirements (characterised by parameters like bandwidth, error probab...

Rarely has there been as challenging and exciting a time for research in computer architecture as now. While, the proverbial Moore’s law has consistently helped architects integrate more and more silicon transistors in a single die, device constraints of power, heat, and reliability has forced the computer industry to shift focus from single processor core performance to instantiating multiple ...

As silicon device scaling trends have simultaneously increased transistor density while reducing component costs, architectures incorporating multiple communicating components are becoming more common. In these systems, networks-on-chip (NOCs) connect the components for communication and NOC design is critical to the performance and efficiency of the system. Typically, in NOC design traditional...

SoC communication infrastructures, such as the Æthereal network on chip (NoC), will play a central role in integrating IPs with diverse communication requirements. To achieve a compositional and predictable system design, it is essential to reduce uncertainties in the interconnect, such as throughput and latency. In our NoC, these uncertainties are eliminated by providing guaranteed throughput ...

A new NoC (network on chip) architecture using lossless data compression and decompression to improve the performance and power efficiency of the on-chip interconnect is proposed. In the proposed NoC scheme, the sender compresses the data to be transferred in order to reduce the number of data packets and the receiver decompresses the encoded data to restore the original data. For the lossless ...

— The architecture for on chip network design using dynamic reconfiguration is a solution to Communication Interfaces, Chip cost ,Quality of Service, guarantee flexibility of the network. The proposed architecture dynamically configure itself with respect to Hardware Modules such as routers, Packet based Switch and data Packet size by changing the communication conditions and its requirements a...

Network-on-Chip (NoC) is the interconnection platform that answers the requirements of the modern on-Chip design. Small optimizations in NoC router architecture can show a significant improvement in the overall performance of NoC based systems. Power consumption, area overhead and the entire NoC performance is influenced by the router buffers. Resource sharing for on-chip network is critical to...

This paper introduces a new approach for a network on chip (NOC) design which is based on a NlogN interconnect topology. The intended application area for the NOC is the real-time communication of multiprocessors that are hosted by a single Field Programmable Gate Array (FPGA). The proposed NOC is an on-chip multistage interconnection network for which an upper limit can be guaranteed that is a...

3D Network on Chip (NoC) has emerged as a new platform to meet the performance requirements and scaling challenges of System on Chip. More investigations require addressing challenges in multiport topologies, minimizing foot printing of nodes and interconnections of wires. This paper discusses multi-port NoC topologies and routing in 2D hexagonal and 3D mesh NoC. Deadlock free routing for 2D he...

With the increasing number of on-chip components and the critical requirement for processing power, Chip Multiprocessor (CMP) has gained wide acceptance in both academia and industry during the last decade. However, the conventional bus-based onchip communication schemes suffer from very high communication delay and low scalability in large scale systems. Network-on-Chip (NoC) has been proposed...